FDC642P Fairchild Semiconductor, FDC642P Datasheet - Page 2

• Manufacturer Part Number: FDC642P
• Description: MOSFET P-CH 20V 4A SSOT-6
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r

Specifications of FDC642P

• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 65 mOhm @ 4A, 4.5V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 4A
• Vgs(th) (max) @ Id: 1.5V @ 250µA
• Gate Charge (qg) @ Vgs: 10nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 640pF @ 10V
• Power - Max: 800mW
• Mounting Type: Surface Mount
• Package / Case: 6-SSOT, SuperSOT-6
• Configuration: Single Quad Drain
• Transistor Polarity: P-Channel
• Resistance Drain-source Rds (on): 0.065 Ohm @ 4.5 V
• Forward Transconductance Gfs (max / Min): 9 S
• Drain-source Breakdown Voltage: 20 V
• Gate-source Breakdown Voltage: +/- 8 V
• Continuous Drain Current: 4 A
• Power Dissipation: 1600 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2010 Fairchild Semiconductor Corporation
FDC642P Rev.C2
Electrical Characteristics
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Notes:
1: R
2: Pulse Test: Pulse Width<300 us, Duty Cycle<2.0%.
BV
∆BV
I
I
V
r
g
C
C
C
t
t
t
t
Q
Q
Q
I
V
DSS
GSS
∆V
d(on)
r
d(off)
f
S
DS(on)
FS
GS(th)
SD
∆T
∆T
iss
oss
rss
a. 78
b. 156
g
gs
gd
R
Symbol
θJA
DSS
θJC
GS(th)
DSS
J
J
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
is guaranteed by design while R
°C/W when mounted on a 1 in
°C/W when mounted on a minimum pad of 2 oz copper.
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
Maximum Continuous Drain-Source Diode Forward Current
Source-Drain Diode Forward Voltage
2
Parameter
θCA
pad of 2 oz copper.
is determined by the user’s board design.
T
J
= 25°C unless otherwise noted
V
V
I
V
V
V
T
V
V
V
V
I
I
V
V
V
f = 1 MHz
D
D
D
V
J
GS
GS
GS
GS
DS
DD
GS
DD
GS
DS
GS
DS
GS
= -250 µA, referenced to 25°C
= -250 µA, V
= -250 µA, referenced to 25°C
= 125°C
= V
= -4.5 V, I
= -2.5 V, I
= -4.5 V, I
= -5 V, I
= -10 V, I
= -16 V, V
= -10 V, I
= -4.5 V, R
= --4.5 V
= ±8 V, V
= -10 V, V
= 0 V, I
2
DS
Test Conditions
, I
D
D
S
D
D
= -1.3 A
DS
= -250 µA
D
D
D
= -4.0 A
= -4 A
GS
GS
GS
GEN
= -1 A,
= -4.0 A
= -3.2 A
= -4.0 A,
= 0 V
= 0 V
= 0 V,
= 0 V
= 6 Ω
(Note 2)
-0.4
Min
-20
-0.7
700
-0.6
110
120
1.1
3.0
Typ
2.5
95
52
45
55
62
15
11
-13
6
7
-1.3
-1.5
925
150
145
-1.2
Max
100
190
±10
12
14
83
16
65
90
www.fairchildsemi.com
-1
mV/°C
mV/°C
Units
mΩ
pF
pF
pF
nC
nC
nC
µA
µA
ns
ns
ns
ns
A
V
V
S
V