DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 94

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 4: Output Frequency of OC4 (OFREQ4[3:0]). This field specifies the frequency of output clock OC4.
The frequencies of the T0 APLL and T4 APLL are configured in the
Digital2 frequencies are configured in the
by the value of the OCR5.AOF4 bit.
AOF4 = 0: (standard decodes)
AOF4 = 1: (alternate decodes)
Bits 3 to 0: Output Frequency of OC3 (OFREQ3[3:0]). This field specifies the frequency of output clock OC3.
The frequencies of the T0 APLL and T4 APLL are configured in the
Digital2 frequencies are configured in the
by the value of the OCR5.AOF3 bit.
AOF3 = 0: (standard decodes)
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = Digital2 (see
0100 = Digital1 (see
0101 = T0 APLL frequency divided by 48
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequency divided by 4
1011 = T4 APLL frequency divided by 2
1100 = T4 APLL frequency divided by 48
1101 = T4 APLL frequency divided by 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequency divided by 4
0000 = Output disabled (i.e., low)
0001 = T0 APLL frequency divided by 2
0010 = T0 APLL frequency
0011 = T4 APLL frequency divided by 10
0100 = T0 APLL2 frequency divided by 10
0101 = T0 APLL2 frequency divided by 2
0110 = T0 APLL2 frequency
0111 = T4 selected reference (after dividing)
1000 = T0 selected reference (after dividing)
1001–1111 = undefined
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = Digital2 (see
0100 = Digital1 (see
0101 = T0 APLL frequency divided by 48
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
7
0
Table
Table
Table
Table
OFREQ4[3:0]
6
0
OCR2
Output Configuration Register 2
61h
7-8)
7-7)
7-8)
7-7)
MCR7
MCR7
5
0
register. See Section 7.8.2.3. The decode of this field is controlled
register. See Section 7.8.2.3. The decode of this field is controlled
4
0
T0CR1
T0CR1
3
0
and
and
T4CR1
T4CR1
2
0
OFREQ3[3:0]
registers. The Digital1 and
registers. The Digital1 and
1
0
94 of 136
0
0