DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 100

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: T4 Measure T0 Phase (T4MT0). When this bit is set to 1 the T4 DPLL goes to the free-run mode, and the T4
phase detector is configured to measure the phase difference between the selected T0 DPLL input clock and the
selected the T4 DPLL input clock. See Section 7.7.10.
Bit 6: T4 APLL Source from T0 (T4APT0). When this bit is set to 0, the T4 APLL DFS is connected to the T4
DPLL, and T4CR1:T4FREQ configures the T4 APLL DFS frequency. The T4 APLL DFS frequency affects the
frequency of the T4 APLL which in turn affects the available output frequencies on the output clock pins (see the
OCR
and the frequency of the T4 APLL DFS is configured by the T0CR1:T0FT4[2:0] field below. See Section 7.8.2.
Bits 5 to 3: T0 Frequency to T4 APLL (T0FT4[2:0]). When the T4APT0 bit is set to 1, this field specifies the
frequency of the T4 APLL DFS. This frequency can be different than the frequency specified by T0CR1:T0FREQ.
See Section 7.8.2.
Bits 2 to 0: T0 DPLL Output Frequency (T0FREQ[2:0]). This field configures the T0 APLL DFS frequency. The
T0 APLL DFS frequency affects the frequency of the T0 APLL, which in turn affects the available output
frequencies on the output clock pins (see the
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
registers). When this bit is set to 1, the T4 APLL DFS is connected to the T0 DPLL rather than the T4 DPLL,
0 = Normal operation for the T4 path.
1 = Enable T4-measure-T0-phase mode.
0 = T4 APLL locks to T4 DPLL.
1 = T4 APLL locks to T0 DPLL.
T0FREQ
T0FT4
000 =
001 =
010 =
011 =
100 =
101 =
110 =
111 =
000 =
001 =
010 =
011 =
100 =
101 =
110 =
111 =
T4MT0
7
0
T4 APLL DFS FREQUENCY
T0 APLL DFS FREQUENCY
25.248MHz (4 x 6312kHz)
25.248MHz (4 x 6312kHz)
62.500MHz (GbE  16)
37.056MHz (24 x DS1)
24.704MHz (16 x DS1)
24.576MHz (12 x E1)
32.768MHz (16 x E1)
62.500MHz (GbE  16)
37.056MHz (24 x DS1)
24.704MHz (16 x DS1)
24.576MHz (12 x E1)
32.768MHz (16 x E1)
T4APT0
{unused value}
{unused value}
6
1
77.76MHz
77.76MHz
T0CR1
T0 DPLL Configuration Register 1
65h
5
0
OCR
T0FT4[2:0]
registers). See Section
4
0
T4 APLL FREQUENCY (4 x T4 APLL DFS)
T0 APLL FREQUENCY (4 x T0 APLL DFS)
100.992MHz (16 x 6312kHz)
100.992MHz (16 x 6312kHz)
311.04MHz (4 x 77.76MHz)
311.04MHz (4 x 77.76MHz)
148.224MHz (96 x DS1)
148.224MHz (96 x DS1)
250.000MHz (GbE  4)
250.000MHz (GbE  4)
98.816MHz (64 x DS1)
98.816MHz (64 x DS1)
131.072MHz (64 x E1)
131.072MHz (64 x E1)
98.304MHz (48 x E1)
98.304MHz (48 x E1)
3
1
{unused value}
{unused value}
7.8.2.
2
0
T0FREQ[2:0]
0
1
100 of 136
1
0