DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 52

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

8.
The DS3104-SE has an overall address range from 000h to 1FFh.
In each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “—“ are
reserved and must be written with 0. Writing other values to these registers may put the device in a factory test
mode resulting in undefined operation. Bits labeled “0” or “1” must be written with that value for proper operation.
Register fields with underlined names are read-only fields; writes to these fields have no effect. All other fields are
read-write. Register fields are described in detail in the register descriptions that follow
Note: Systems must be able to access the entire address range from 0 to 01FFh. Proper device initialization
requires a sequence of writes to addresses in the range 0180-01FFh.
8.1
The device has two types of status bits. Real-time status bits are read-only and indicate the state of a signal at the
time it is read. Latched status bits are set when a signal changes state (low-to-high, high-to-low, or both, depending
on the bit) and cleared when written with a logic 1 value. Writing a 0 has no effect. When set, some latched status
bits can cause an interrupt request on the INTREQ pin if enabled to do so by corresponding interrupt enable bits.
ISR#.LOCK# are special-case latched status bits because they cannot create an interrupt request on the INTREQ
pin and a “write 0” is needed to clear them.
8.2
Configuration fields are read-write. During reset, each configuration field reverts to the default value shown in the
register definition. Configuration register bits marked “—” are reserved and must be written with 0.
8.3
Multiregister fields—such as FREQ[18:0] in registers FREQ1, FREQ2, and FREQ3—must be handled carefully to
ensure that the bytes of the field remain consistent. A write access to a multiregister field is accomplished by
writing all the registers of the field in any order, with no other accesses to the device in between. If the write
sequence is interrupted by another access, none of the bytes are written and the MSR4:MRAA latched status bit is
set to indicate the write was aborted. A read access from a multiregister field is accomplished by reading the
registers of the field in any order, with no other accesses to the device in between. When one register of a
multiregister field is read, the other register(s) in the field are frozen until after they are all read. If the read
sequence is interrupted by another access, the registers of the multibyte field are unfrozen and the MSR4:MRAA
bit is set to indicate the read was aborted. For best results, interrupt servicing should be disabled in the
microprocessor before a multiregister access and then enabled again after the access is complete. The
multiregister fields are:
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
MCLKFREQ[15:0]
HARDLIM[9:0]
OFFSET[15:0]
PHASE[15:0]
FREQ[18:0]
DIVN[15:0]
FIELD
Register Descriptions
Status Bits
Configuration Fields
Multiregister Fields
FREQ1, FREQ2,
OFFSET1,
PHASE1,
DLIMIT1,
MCLK1,
DIVN1,
REGISTERS
MCLK2
DLIMIT2
DIVN2
OFFSET2
PHASE2
FREQ3
0Ch, 0Dh, 07h
ADDRESSES
3Ch, 3Dh
41h, 42h
46h, 47h
70h, 71h
77h, 78h
Table 8-1
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Read Only
in Section
TYPE
Table
8.4
shows the register map.
8-1.
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