DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 31

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

7.7.3 Bandwidth
The bandwidth of the T4 DPLL is configured in the
The bandwidth of the T0 DPLL is configured in the
400Hz. The AUTOBW bit in the
T0 DPLL uses the T0ABW bandwidth during acquisition (not phase-locked) and the T0LBW bandwidth when
phase-locked. When AUTOBW = 0 the T0 DPLL uses the T0LBW bandwidth all the time, both during acquisition
and when phase-locked.
When LIMINT = 1 in the
minimum or maximum frequency. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in.
7.7.4 Damping Factor
The damping factor for the T0 DPLL is configured in the DAMP field of the
factor of the T4 DPLL is configured in the DAMP field of the
both DPLLs are chosen to give a maximum jitter/wander gain peak of approximately 0.1dB. Available settings are a
function of DPLL bandwidth (configured in the T4BW, T0ABW, and
Table 7-4. Damping Factors and Peak Jitter/Wander Gain
7.7.5 Phase Detectors
Phase detectors are used to compare a PLL’s feedback clock with its input clock. Several phase detectors are
available in the T0 and T4 DPLLs:
These detectors can be used in combination to give fine phase resolution combined with large jitter tolerance. As
with the rest of the DPLL logic, the phase detectors operate at input frequencies up to 77.76MHz. The multicycle
phase detector detects and remembers phase differences of many cycles (up to 8191UI). When locking to 8kHz or
lower, the normal phase/frequency detectors are always used.
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
BANDWIDTH
70 to 400
0.1 to 4
(Hz)
18
35



8
Phase/frequency detector (PFD)
Early/late phase detector (PD2) for fine resolution
Multicycle phase detector (MCPD) for large input jitter tolerance and/or faster lock times
DAMP[2:0]
1, 2, 3, 4, 5
2, 3, 4, 5
VALUE
3, 4, 5
4, 5
1
1
2
1
2
3
1
2
3
4
5
MCR9
register, the DPLL’s integral path is limited (i.e., frozen) when the DPLL reaches
MCR9
DAMPING
FACTOR
register controls automatic bandwidth selection. When AUTOBW = 1, the
2.5
1.2
2.5
1.2
2.5
1.2
2.5
10
10
20
5
5
5
5
5
T4BW
T0ABW
GAIN PEAK
register to be 18Hz to 70Hz.
(dB)
0.06
0.06
0.03
0.1
0.2
0.1
0.4
0.2
0.1
0.4
0.2
0.1
0.4
0.2
0.1
and
T4CR2
T0LBW
T0LBW
register. The reset default damping factors for
registers for various values from 0.1Hz to
registers). See
T0CR2
register, while the damping
Table
7-4.
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