DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 117

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DS3104GN

Manufacturer Part Number
DS3104GN
Description
Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
Manufacturer
Maxim Integrated Products
Datasheet

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9.
9.1
The DS3104-SE supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional
public instructions included are HIGHZ, CLAMP, and IDCODE.
contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture:
The TAP has the necessary interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS. Details on these pins
can be found in Table 6-5. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.1-
1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 9-1. JTAG Block Diagram
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
JTAG Test Access Port and Boundary Scan
JTAG Description
Test Access Port (TAP)
TAP Controller
Instruction Register
50k
JTDI
50k
JTMS
IDENTIFICATION
TEST ACCESS PORT
INSTRUCTION
BOUNDARY
REGISTER
REGISTER
REGISTER
REGISTER
CONTROLLER
BYPASS
DEVICE
SCAN
Bypass Register
Boundary Scan Register
Device Identification Register
JTCLK
50k
JTRST
Figure 9-1
SELECT
TRI-STATE
shows a block diagram. The DS3104-SE
JTDO
117 of 136

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