DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 102
DS3104GN
Manufacturer Part Number
DS3104GN
Description
Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3104GN.pdf
(136 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 4: Reserved Bit 1 (RSV1). This bit is reserved for future use, it can be written to and read back.
Bits 3 to 0: T0 DPLL Acquisition Bandwidth (T0ABW[3:0]). This field configures the bandwidth of the T0 DPLL
when acquiring lock. When AUTOBW = 0 in the
for locked operation. When AUTOBW = 1,
used for locked operation. See Section 7.7.3.
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
1000 = 0.1Hz
1001 = 0.3Hz
1010 = 0.6Hz
1011 = 1.2Hz
1100 = 2.5Hz
1101 = 4Hz
1110 = 8Hz
1111 = 18Hz (default)
0000 = 35Hz
0001 = 70Hz
0010 = {unused values, undefined}
0011 = 18Hz
0100 = 120Hz
0101 = 250Hz
0110 = 400Hz
0111 = 18Hz
—
7
0
—
6
0
T0ABW
T0 DPLL Acquisition Bandwidth Register
69h
—
5
0
T0ABW
MCR9
bandwidth is used for acquisition while T0LBW bandwidth is
RSV1
4
0
register, the T0LBW bandwidth is used for acquisition and
3
1
2
1
T0ABW[3:0]
1
1
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0
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