DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 108

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: The OFFSET1 and OFFSET2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: Phase Offset (OFFSET[7:0]). The full 16-bit OFFSET[15:0] field spans this register and the
register. OFFSET is a two’s-complement signed integer that specifies the desired phase offset between the output
clocks and the selected input reference. The phase offset in picoseconds is equal to OFFSET[15:0] 
actual_internal_clock_period / 2
equation simplifies to OFFSET[15:0]  6.279ps. If, however, the DPLL is locked to a reference whose frequency is
+1ppm from ideal, for example, then the actual internal clock period is 1ppm shorter and the phase offset is 1ppm
smaller. When the OFFSET field is written, the phase of the output clocks is automatically ramped to the new offset
value to avoid loss of synchronization. To adjust the phase offset without changing the phase of the output clocks,
use the recalibration process enabled by FSCR3:RECAL. The OFFSET field is ignored when phase build-out is
enabled (PBOEN = 1 in the
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Phase Offset (OFFSET[15:8]). See the
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
7
0
7
0
MCR10
6
0
6
0
11
OFFSET1
Phase Offset Register 1
70h
OFFSET2
Phase Offset Register 2
71h
. If the internal clock is at its nominal frequency of 77.76MHz, the phase offset
register) and when the DPLL is not locked. See Section 7.7.8.
5
0
5
0
OFFSET1
4
0
4
0
OFFSET[15:8]
OFFSET[7:0]
register description.
3
0
3
0
2
0
2
0
1
0
1
0
108 of 136
OFFSET2
0
0
0
0