DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 65

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Activity Alarm for Input Clock 2 (ACT2). This real-time status bit is set to 1 when the leaky bucket
accumulator for IC2 reaches the alarm threshold specified in the
BUCKET field of ICR1). An activity alarm clears the IC2 status bit in the
clock. See Section 7.5.2.
Bit 4: Phase-Lock Alarm for Input Clock 2 (LOCK2). This status bit is set to 1 if IC2 is the selected reference
and the T0 DPLL cannot phase lock to IC2 within the duration specified in the
seconds). A phase-lock alarm clears the IC2 status bit in VALSR1, invalidating the IC2 clock. If LKATO = 1 in
MCR3, LOCK2 is automatically cleared after a timeout period of 128 seconds. LOCK2 is a read/write bit. System
software can clear LOCK4 by writing 0 to it, but writing 1 is ignored. See Section 7.7.1.
Bit 1: Activity Alarm for Input Clock 1 (ACT1). This bit has the same behavior as the ACT2 bit but for the IC1
input clock.
Bit 0: Phase-Lock Alarm for Input Clock 1 (LOCK1). This bit has the same behavior as the LOCK2 bit but for the
IC1 input clock.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Activity Alarm for Input Clock 4 (ACT4). This real-time status bit is set to 1 when the leaky bucket
accumulator for IC4 reaches the alarm threshold specified in the
BUCKET field of ICR4). An activity alarm clears the IC4 status bit in the
clock. See Section 7.5.2.
Bit 4: Phase-Lock Alarm for Input Clock 4 (LOCK4). This status bit is set to 1 if IC4 is the selected reference
and the T0 DPLL cannot phase lock to IC4 within the duration specified in the
seconds). A phase-lock alarm clears the IC4 status bit in VALSR1, invalidating the IC4 clock. If LKATO = 1 in
MCR3, LOCK4 is automatically cleared after a timeout period of 128 seconds. LOCK4 is a read/write bit. System
software can clear LOCK4 by writing 0 to it, but writing 1 is ignored. See Section 7.7.1.
Bit 1: Activity Alarm for Input Clock 3 (ACT3). This bit has the same behavior as the ACT4 bit but for the IC3
input clock.
Bit 0: Phase-Lock Alarm for Input Clock 3 (LOCK3). This bit has the same behavior as the LOCK4 bit but for the
IC3 input clock.
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
—
—
7
0
7
0
—
—
6
0
6
0
ISR1
Input Status Register 1
10h
ISR2
Input Status Register 2
11h
ACT2
ACT4
5
1
5
1
LOCK2
LOCK4
4
0
4
0
LBxU
LBxU
—
—
3
0
3
0
register (where x in LBxU is specified in the
register (where x in LBxU is specified in the
VALSR1
VALSR1
—
—
2
0
2
0
PHLKTO
PHLKTO
register, invalidating the IC2
register, invalidating the IC4
register (default = 100
register (default = 100
ACT1
ACT3
1
1
1
1
65 of 136
LOCK1
LOCK3
0
0
0
0