DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 67

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DS3104GN

Manufacturer Part Number
DS3104GN
Description
Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
Manufacturer
Maxim Integrated Products
Datasheet

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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Holdover Frequency Ready (HORDY). This latched status bit is set to 1 when the T0 DPLL has a holdover
value that has been averaged over the 1-second holdover averaging period. HORDY is cleared when written with a
1. When HORDY is set it can cause an interrupt request on the INTREQ pin if the HORDY interrupt enable bit is
set in the
Bit 5: Multiregister Access Aborted (MRAA). This latched status bit is set to 1 when a multibyte access (read or
write) is interrupted by another access to the device. MRAA is cleared when written with a 1. MRAA cannot cause
an interrupt to occur. See Section 8.3.
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
IER4
register. See Section 7.7.1.6.
7
0
HORDY
6
0
MSR4
Master Status Register 4
17h
MRAA
5
0
4
0
3
0
2
0
1
0
67 of 136
0
0

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