HUFA76504DK8T Fairchild Semiconductor, HUFA76504DK8T Datasheet - Page 9

• Manufacturer Part Number: HUFA76504DK8T
• Description: MOSFET N-CHAN 80V 2.3A 8-SOIC
• Manufacturer: Fairchild Semiconductor
• Series: UltraFET™r

Specifications of HUFA76504DK8T

• Fet Type: 2 N-Channel (Dual)
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 200 mOhm @ 2.5A, 10V
• Drain To Source Voltage (vdss): 80V
• Current - Continuous Drain (id) @ 25° C: 2.3A
• Vgs(th) (max) @ Id: 3V @ 250µA
• Gate Charge (qg) @ Vgs: 10nC @ 10V
• Input Capacitance (ciss) @ Vds: 270pF @ 25V
• Power - Max: 2.5W
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Configuration: Dual Dual Drain
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 0.173 Ohms
• Forward Transconductance Gfs (max / Min): 0.00008 S
• Drain-source Breakdown Voltage: 80 V
• Gate-source Breakdown Voltage: +/- 16 V
• Continuous Drain Current: 2.3 A
• Power Dissipation: 2.5 W
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PSPICE Electrical Model
.SUBCKT HUFA76504DK8 2 1 3 ;
CA 12 8 2.5e-10
CB 15 14 3e-10
CIN 6 8 2.6e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 100.6
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 4.21e-10
LSOURCE 3 7 1.28e-10
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.1e-1
RGATE 9 20 5.74e1
RLDRAIN 2 5 10
RLGATE 1 9 42.1
RLSOURCE 3 7 12.8
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 5.72e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*12),3.7))}
.MODEL DBODYMOD D (IS = 3.1e-13 N = 1.03 RS = 4.2e-2 TRS1 = 3e-4 TRS2 = 1.3e-6 CJO = 6.82e-10 TT = 3.3e-8 M = 0.8 XTI = 4)
.MODEL DBREAKMOD D (RS = 1.65 TRS1 = 1e-3 TRS2 = -9e-6)
.MODEL DPLCAPMOD D (CJO = 1.7e-10 IS = 1e-30 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 2.2 KP = 1.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 5.74e1)
.MODEL MSTROMOD NMOS (VTO = 2.56 KP = 18 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.94 KP = 0.04 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 5.74e2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.12e-3 TC2 = -3e-7)
.MODEL RDRAINMOD RES (TC1 = 9e-3 TC2 = 2e-5)
.MODEL RSLCMOD RES (TC1 = 2.8e-3 TC2 = 1.9e-5)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -3e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.5e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF= -4)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
GATE
1
RLGATE
LGATE
REV 18 January 2001
9
RGATE
CA
12
20
+
EVTEMP
S1A
S1B
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
6
8
6
RSLC2
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
51
5
5
MSTRO
14
+
-
51
21
RDRAIN
RSLC1
50
ESLC
16
8
MMED
8
EBREAK
IT
DBREAK
RSOURCE
17
MWEAK
RVTHRES
RBREAK
11
+
-
17
18
7
+
-
18
22
RVTEMP
19
RLSOURCE
VBAT
DBODY
LSOURCE
RLDRAIN
LDRAIN
SOURCE
DRAIN
Rev. A, June 4, 2001
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3