EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 85

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Figure 4–25. Mixed Port Read-During-Write: Old Data Mode
Altera Corporation-Preliminary
March 2007
q_b (asynch)
address_b
address_a
clk_a&b
wren_a
rden_a
data_a
f
A
Refer to the RAM Megafunction User Guide for more details on how to
implement the desired behavior.
Figure 4–25
read-during-write behavior for the “Old Data” mode. In “Don't Care”
mode, the old data shown in the figure is simply replaced with “Don't
Care”.
Cyclone III M9K memory blocks do not support mixed-port
read-during-write when two different clocks are used in a dual-port
RAM. The output value is unknown during a dual-clock mixed-port
read-during-write operation.
Conflict Resolution
When using the memory blocks in true dual-port mode, it is possible to
attempt two write operations to the same memory location (address).
Since there is no conflict resolution circuitry built into the memory blocks,
this results in unknown data being written to that location. Therefore, you
need to implement conflict-resolution logic external to the memory block.
a (old data)
a
a
B
shows a sample functional waveform of mixed port
A
C
B
D
b (old data)
Cyclone III Device Handbook, Volume 1
E
b
b
D
F
Design Considerations
E
4–31