EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 364

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

SEU Mitigation in Cyclone III Devices
Configuration
Error Detection
User Mode
Error Detection
13–2
Cyclone III Device Handbook, Volume 1
There are two CRC error checks:
■
■
For more information, refer to
page 13–2
In configuration mode, a frame-based CRC is stored within the
configuration data and contains the CRC value for each data frame.
During configuration, the FPGA calculates the CRC value based on the
frame of data that is received and compares it against the frame CRC
value in the data stream. Configuration continues until either the device
detects an error or all the values are calculated.
For Cyclone III devices, the CRC is computed by the Quartus II software
and downloaded into the device as part of the configuration bit stream.
These devices store the CRC in the 32-bit storage register at the end of the
configuration mode.
Soft errors are changes in a configuration random-access memory
(CRAM) bit state due to an ionizing particle. All Cyclone series devices
have built-in error detection circuitry to detect data corruption by soft
errors in the CRAM cells.
This error detection capability continuously computes the CRC of the
configured CRAM bits based on the contents of the device and compares
it with the pre-calculated CRC value obtained at the end of the
configuration. If the CRCs match, there is no error in the current
configuration CRAM bits. The process of error detection continues until
the device is reset (by setting nCONFIG to low).
The Cyclone III device error detection feature does not check memory
blocks and I/O buffers. These device memory blocks support parity bits
that are used to check the contents of memory blocks for any error. The
I/O buffers are not verified during error detection because these bits use
flip-flops as storage elements that are more resistant to soft errors. Similar
flip-flops are used to store the pre-calculated CRC and other error
detection circuitry option bits.
The error detection circuitry in Cyclone III devices uses a 32-bit CRC IEEE
802 standard and 32-bit polynomial as the CRC generator. Therefore, a
single 32-bit CRC calculation is performed by the device. If a soft error
does not occur, the resulting 32-bit signature value is 0x000000, which
One always during configuration
A second optional CRC error check runs in the background in user
mode
and
“User Mode Error Detection” on page
“Configuration Error Detection” on
Altera Corporation-Preliminary
13–2.
March 2007