EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 29

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EP3C16F256I7

Manufacturer Part Number
EP3C16F256I7
Description
Cyclone III
Manufacturer
Altera
Datasheet

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Reference and
Ordering
Information
Altera Corporation-Preliminary
March 2007
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SEU Mitigation
Cyclone III devices offer built-in error detection circuitry to detect data
corruption due to soft errors in the configuration random-access memory
(CRAM) cells. This feature allows all CRAM contents to be read and
verified to match a configuration-computed CRC value. The Quartus II
software activates the Cyclone III built-in 32-bit CRC checker.
For more information, refer to the SEU Mitigation chapter in the
Cyclone III Device Handbook.
JTAG Boundary Scan Testing
Cyclone III devices support the JTAG IEEE Std. 1149.1 specification. The
Boundary-Scan Test (BST) architecture offers the capability to test pin
connections without using physical test probes and capture functional
data while a device is operating normally. Boundary-scan cells in the
Cyclone III device can force signals onto pins or capture data from pins or
logic array signals. Forced test data is serially shifted into the
boundary-scan cells. Captured data is serially shifted out and externally
compared to expected results. In addition to BST, you can use the IEEE
Std. 1149.1 controller for Cyclone III device in-circuit reconfiguration
(ICR).
For more information, refer to IEEE 1149.1 (JTAG) Boundary-Scan Testing
chapter in the Cyclone III Device Handbook.
Figure 1–2
describes the ordering codes for Cyclone III devices.
Cyclone III Device Handbook, Volume 1
Reference and Ordering Information
1–13

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