EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 139

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Figure 6–23. PLL Reconfiguration Scan Chain
Altera Corporation-Preliminary
March 2007
CONFIGUPDATE
SCANDATAOUT
SCANCLKENA
SCANDONE
SCANDATA
SCANCLK
ARESET
Dn_old
Dn
The procedure to reconfigure the PLL counters is shown below:
1.
2.
3.
4.
5.
6.
7.
Figure 6–23
feature.
The scanclkena signal is asserted at least one scanclk cycle prior
to shifting in the first bit of scandata (Dn).
Serial data (scandata) is shifted into the scan chain on the 2
rising edge of scanclk.
After all 144 bits have been scanned into the scan chain, the
scanclkena signal is de-asserted to prevent inadvertent shifting of
bits in the scan chain.
The configupdate signal is asserted for one scanclk cycle to
update the PLL counters with the contents of the scan chain.
The scandone signal goes high indicating that the PLL is being
reconfigured. A falling edge indicates that the PLL counters have
been updated with new settings.
Reset the PLL using the areset signal if you make any changes to
the M, N counters or the Icp, R, C settings. You do not need to reset
the PLL when reconfiguring just the post-scale counters.
Steps 1 through 5 can be repeated to reconfigure the PLL any
number of times.
shows a functional simulation of the PLL reconfiguration
Cyclone III Device Handbook, Volume 1
D0_old
D0
LSB
Dn
PLL Reconfiguration
nd
6–39