EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 128

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
Figure 6–16. Automatic Clock Switchover Circuit Block Diagram
6–28
Cyclone III Device Handbook, Volume 1
inclk1
inclk0
muxout
Automatic Clock Switchover
Cyclone III device PLLs support a fully configurable clock switchover
capability.
built into the PLL. When the current reference clock is not present, the
clock sense block automatically switches to the backup clock for PLL
reference. The clock switchover circuit also sends out three status
signals—clkbad[0], clkbad[1], and activeclock—from the PLL to
implement a custom switchover circuit. You can select a clock source at
the backup clock by connecting it to the inclk1 port of the PLL in your
design.
There are two possible ways to use the clock switchover feature.
■
Use the switchover circuitry for switching from inclk0 to inclk1
running at the same frequency. For example, in applications that
require a redundant clock with the same frequency as the reference
clock, the switchover state machine generates a signal that controls
the multiplexer select input shown in
inclk1 becomes the reference clock for the PLL. This automatic
switchover can switch back and forth between inclk0 and inclk1
clocks any number of times, when one of the two clocks fails and the
other clock is available.
clksw
Figure 6–16
n Counter
Sense
Clock
shows the block diagram of the switchover circuit
refclk
Switchover
Machine
State
PFD
Figure
Altera Corporation- Preliminary
6–16. In this case,
clkswitch
Provides manual
switchover support
fbclk
clkbad0
clkbad1
Activeclock
March 2007