EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 183

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
Notes to
(1)
(2)
(3)
Table 7–8. Acceptable Input and Output Levels (1), (2),
1.2 V
1.5 V
1.8 V
2.5 V
3.0 V
3.3 V
Bank
V
(V)
CCIO
These input values overdrive the input buffer, so the pin leakage current is slightly higher than the default value.
Because the input level does not drive to the rail, the input buffer does not completely shut off. The I/O current is
slightly higher than the default value.
The PCI clamping diode must be enabled for input signals at 3.0 V or 3.3V.
Table
1.2 V
v
7–8:
f
1.5 V
v(2)
v
v
1.8 V
Input Signal
v
(1)
Table 7–8
corresponding bank voltage.
For more information about Cyclone III I/O interface support, refer to
AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS
I/O Systems.
High-Speed Differential Interfaces
Cyclone III devices can transmit and receive data through LVDS signals.
For the LVDS transmitter and receiver, the Cyclone III device's input and
output pins support serialization and de-serialization through internal
logic.
The reduced swing differential signaling (RSDS) and mini-LVDS
standards are derivatives of the LVDS standard. The RSDS and
mini-LVDS I/O standards are similar in electrical characteristics to LVDS,
but have a smaller voltage swing and therefore provide increased power
benefits and reduced electromagnetic interference (EMI).
The point-to-point differential signalling (PPDS) standard is the next
generation of RSDS standard introduced by National Semiconductor
Corporation. Cyclone III devices meet the National Semiconductor
Corporation PPDS Interface Specification and support the PPDS standard
for outputs only. All the I/O banks of Cyclone III devices support the
PPDS standard for output pins only.
v
v
2.5 V
v
(2)
(2)
shows the acceptable input and output levels with
v
v
v
3.0 V
(3)
(3)
(3)
v
v
v
3.3 V
(3)
(3)
(3)
(3)
1.2 V
v
Cyclone III Device Handbook, Volume 1
1.5 V
v
Output Signal
1.8 V
v
2.5 V
v
3.0 V
v
I/O Banks
3.3 V
v
7–31