EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 213

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Software
Overview
Altera Corporation-Preliminary
March 2007
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Use the following general guidelines for improved signal quality:
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For PCB layout guidelines, refer to AN 224: High-Speed Board Layout
Guidelines and AN 315: Guidelines for Designing High-Speed FPGA PCBs.
Cyclone III device high-speed I/O system interfaces are created in core
logic by a Quartus II software megafunction, because they do not have a
dedicated circuit for the serializer and deserializer (SERDES). Cyclone III
devices use the I/O registers and logic element (LE) registers to improve
the timing performance and support the SERDES. Altera Quartus II
software allows you to design your high-speed interfaces using its altlvds
megafunction. This megafunction implements either a high-speed
deserializer receiver or a high-speed serializer transmitter. There is a list
of parameters in the megafunction you can set to customize your SERDES
based on your design requirements. The megafunction is optimized to
use the Cyclone III resources to create the high-speed I/O interfaces in the
most effective manner.
Base board designs on controlled differential impedance. Calculate
and compare all parameters, such as trace width, trace thickness, and
the distance between two differential traces.
Maintain equal distance between traces in differential I/O standard
pairs as much as possible. Routing the pair of traces close to each
other maximizes the common-mode rejection ratio (CMRR).
Longer traces have more inductance and capacitance. These traces
should be as short as possible to limit signal integrity issues.
Place termination resistors as close to receiver input pins as possible.
Use surface mount components.
Avoid 90° corners.
Use high-performance connectors.
Design backplane and card traces so that trace impedance matches
the impedance of the connector and/or termination.
Keep an equal number of vias for both signal traces.
Create equal trace lengths to avoid skew between signals. Unequal
trace lengths result in misplaced crossing points and decrease system
margins as the channel-to-channel skew (TCCS) value increases.
Limit vias because they cause discontinuities.
Use common bypass-capacitor values such as 0.001, 0.01, and 0.1 μF
to decouple the high-speed PLL power and ground planes.
Keep switching transistor-to-transistor logic (TTL) signals away
from differential signals to avoid possible noise coupling.
Do not route TTL clock signals to areas under or above the
differential signals.
Analyze system-level signals.
Cyclone III Device Handbook, Volume 1
Software Overview
8–23