EP3C16F256I7 Altera, EP3C16F256I7 Datasheet - Page 63

• Manufacturer Part Number: EP3C16F256I7
• Description: Cyclone III
• Manufacturer: Altera

Figure 4–6. Output Latch Asynchronous Clear Waveform
Altera Corporation-Preliminary
March 2007
aclr at latch
aclr
clk
q
f
Mixed Width Support
M9K memory blocks support mixed data widths. When using simple
dual-port, true dual-port, or FIFO modes, mixed width support allows
you to read and write different data widths to a memory block. See
“Memory Modes” on page 4–10
supported per memory mode.
Asynchronous Clear
Cyclone III devices support asynchronous clears for read address
registers, output registers and output latches only. Input registers other
than read address registers are not supported. When applied to output
registers, the asynchronous clear signal clears the output registers. You
can see the effects immediately. If your RAM does not use the output
registers, you can still clear the RAM outputs via the output latch
asynchronous clear.
1
Figure 4–6
1
See the RAM Megafunction User Guide for more details.
There are three ways to reset registers in the M9K blocks: power up the
device, use the aclr signal for output register only, or assert the
device-wide reset signal using the DEV_CLRn option.
a1
Asserting asynchronous clear to the read address register
duringa read operation could corrupt the memory content.
You can selectively enable asynchronous clears per logical
memory via the Quartus II RAM MegaWizard
a2
shows the functional waveform for this feature.
for details on the different widths
Cyclone III Device Handbook, Volume 1
a0
a1
®
.
Overview
4–9