CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 32

• Manufacturer Part Number: CS2000CP-CZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1748; CS2000CP-CZZ

32
8.7.2
8.7.3
8.8
8.8.1
8.8.2
Reserved
7
Function Configuration 2 (Address 17h)
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
Note:
fore, the pin polarity is defined relative to the unlock condition.
Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the currently indexed 32-bit User Defined Ratio when the dynamic ratio based
Hybrid PLL Mode is selected (either manually or automatically, see
Note:
matically), the currently indexed User Defined Ratio will always be interpreted as a 12.20 fixed point value,
regardless of the state of this bit.
AuxLockCfg
0
1
Application:
ClkOutUnl
0
1
Application:
LFRatioCfg
0
1
Application:
RefClkDiv[1:0]
00
01
10
11
Application:
Reserved
AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
When the static ratio based Frequency Synthesizer Mode is selected (either manually or auto-
6
AUX_OUT Driver Configuration
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
“Auxiliary Output” on page 23
Clock Output Enable Status
Clock outputs are driven ‘low’ when PLL is unlocked.
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
“PLL Clock Output” on page 23
Ratio Bit Encoding Interpretation when Input Clock Source is CLK_IN
20.12 - High Multiplier.
12.20 - High Accuracy.
“User Defined Ratio (RUD), Hybrid PLL Mode” on page 19
Reference Clock Input Divider
÷ 4.
÷ 2.
÷ 1.
Reserved.
“Internal Timing Reference Clock Divider” on page 14
Reserved
5
ClkOutUnl
4
LFRatioCfg
3
REF_CLK Frequency Range
32 MHz to 56 MHz (50 MHz with XTI)
16 MHz to 28 MHz
8 MHz to 14 MHz
Reserved
section 5.3.5 on page
2
Reserved
1
CS2000-CP
21).
Reserved
DS761F2
0