CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 24

• Manufacturer Part Number: CS2000CP-CZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1748; CS2000CP-CZZ

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5.6
5.6.1
5.6.2
5.7
6. SPI / I²C CONTROL PORT
The control port is used to access the registers and allows the device to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to device inputs
and outputs. However, to avoid potential interference problems, the control port pins should remain static if no op-
eration is required.
Clock Output Stability Considerations
Required Power Up Sequencing
•
•
Output Switching
CS2000 is designed such that re-configuration of the clock routing functions do not result in a partial clock
period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an
output, changing the auxiliary output source between REF_CLK and CLK_OUT, changing between Fre-
quency Synthesizer and Hybrid PLL Mode, and the automatic disabling of the output(s) during unlock will
not cause a runt or partial clock period.
The following exceptions/limitations exist:
• Enabling/disabling AUX_OUT when AuxOutSrc[1:0] = 11 (unlock indicator).
• Switching AuxOutSrc[1:0] to or from 01 (PLL clock input) and to or from 11 (unlock indicator)
• Changing the ClkOutUnl bit while the PLL is in operation.
When any of these exceptions occur, a partial clock period on the output may result.
PLL Unlock Conditions
Certain changes to the clock inputs and registers can cause the PLL to lose lock which will affect the pres-
ence the clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go un-
locked:
• Changes made to the registers which affect the Fraction-N value that is used by the Frequency Syn-
• Any discontinuities on the Timing Reference Clock, REF_CLK.
• Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature
• Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency.
• Step changes in CLK_IN frequency.
via the control port.
ing the initialization register writes; the order does not matter.
Apply power to the device. The output pins will remain low until the device is configured with a valid ratio
Write the desired operational configurations. The EnDevCfg1 and EnDevCfg2 bits must be set to 1 dur-
–
(Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
thesizer. This includes all the bits shown in
is enabled and the requirements of Clock Skipping are satisfied (see
page
The Freeze bit may be set prior to this step and cleared afterward to ensure all settings take effect
at the same time.
15).
Figure 18 on page
22.
“CLK_IN Skipping Mode” on
CS2000-CP
DS761F2