CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 29

• Manufacturer Part Number: CS2000CP-CZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1748; CS2000CP-CZZ

DS761F2
8.2.3
8.3
8.3.1
8.3.2
8.3.3
RModSel2
7
Device Configuration 1 (Address 03h)
PLL Clock Output Disable (ClkOutDis)
This bit controls the output driver for the CLK_OUT pin.
R-Mod Selection (RModSel[2:0])
Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N.
Ratio Selection (RSel[1:0])
Selects one of the four stored User Defined Ratios for use in the static ratio based Frequency Synthesizer
Mode.
Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
Note:
uration (AuxLockCfg)” on page
ClkOutDis
0
1
Application:
RModSel[2:0]
000
001
010
011
100
101
110
111
Application:
RSel[1:0]
00
01
10
11
Application:
AuxOutSrc[1:0]
00
01
10
11
Application:
RModSel1
When set to 11, AuxLckCfg sets the polarity and driver type. See
6
Output Driver State
CLK_OUT output driver enabled.
CLK_OUT output driver set to high-impedance.
“PLL Clock Output” on page 23
R-Mod Selection
Left-shift R-value by 0 (x 1).
Left-shift R-value by 1 (x 2).
Left-shift R-value by 2 (x 4).
Left-shift R-value by 3 (x 8).
Right-shift R-value by 1 (÷ 2).
Right-shift R-value by 2 (÷ 4).
Right-shift R-value by 3 (÷ 8).
Right-shift R-value by 4 (÷ 16).
“Ratio Modifier (R-Mod)” on page 20
Ratio Selection
Ratio 0.
Ratio 1.
Ratio 2.
Ratio 3.
“User Defined Ratio (RUD), Frequency Synthesizer Mode” on page 19
Auxiliary Output Source
RefClk.
CLK_IN.
CLK_OUT.
PLL Lock Status Indicator.
“Auxiliary Output” on page 23
RModSel0
5
32.
RSel1
4
RSel0
3
AuxOutSrc1
2
“AUX PLL Lock Output Config-
AuxOutSrc0
1
CS2000-CP
EnDevCfg1
0
29