CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 20

• Manufacturer Part Number: CS2000CP-CZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1748; CS2000CP-CZZ

20
5.3.3
5.3.4
Ratio Modifier (R-Mod)
The Ratio Modifier is used to internally multiply/divide the currently addressed R
the register space remain unchanged). The available options for R
page
The R-Mod value selected by RModSel[2:0] is always used in the calculation for the Effective Ratio
(R
its default value of ‘000’, which corresponds to an R-Mod value of 1, thereby effectively disabling the ratio
modifier.
Effective Ratio (R
The Effective Ratio (R
previously described. R
R
To simplify operation the device handles some of the ratio calculation functions automatically (such as
when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need
to be altered to account for internal dividers.
Ratio modifiers which would produce an overflow or truncation of R
if R
12.20 format. In all cases, the maximum and minimum allowable values for R
quency limits for both the input and output clocks as shown in the
page
Selection of the user defined ratio from the four stored ratios is made by using the RSel[1:0] bits unless
auto clock switching is enabled in which case the LockClk[1:0] bits also select the ratio (see
tional-N Source Selection for the Frequency Synthesizer” on page
Referenced Control
Ratio 0-3
RModSel[2:0]
Referenced Control
RSel[1:0]
LockClk[1:0]
EFF
EFF
UD
20.
= R
8.
),
is 1024 an R
.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 31
see “Effective Ratio (REFF)” on page
...............................“Ratio Selection (RSel[1:0])” on page 29
UD
..........................“Lock Clock Ratio (LockClk[1:0])” section on page 30
........................“R-Mod Selection (RModSel[2:0])” section on page 29
•
R
MOD
RModSel[2:0]
MOD
EFF
EFF
Register Location
Register Location
EFF
000
001
010
100
101
011
110
111
of 8 would produce an R
) is an internal calculation comprised of R
)
is calculated as follows:
Table 1. Ratio Modifier
20. If R-Mod is not desired, RModSel[2:0] should be left at
EFF
value of 8192 which exceeds the 4096 limit of the
Ratio Modifier
0.0625
0.125
0.25
0.5
1
2
4
8
21).
EFF
UD
MOD
“AC Electrical Characteristics” on
and the appropriate modifiers, as
should not be used; For example
are summarized in
EFF
UD
are dictated by the fre-
(the Ratio
CS2000-CP
“Manual Frac-
0-3
Table 1 on
DS761F2
stored in