CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 14

• Manufacturer Part Number: CS2000CP-CZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1748; CS2000CP-CZZ

14
5. APPLICATIONS
5.1
5.1.1
Timing Reference Clock Input
The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an
external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL out-
put the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock
directly affects the performance of the PLL and hence the quality of the PLL output.
Internal Timing Reference Clock Divider
The Internal Timing Reference Clock (SysClk) has a smaller maximum frequency than what is allowed on
the XTI/REF_CLK pin. The CS2000 supports the wider external frequency range by offering an internal
divider for RefClk. The RefClkDiv[1:0] bits should be set such that SysClk, the divided RefClk, then falls
within the valid range as indicated in
It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent
upon its configuration as either a crystal connection or external clock input. See the
acteristics” on page 8
For the lowest possible output jitter, attention should be paid to the absolute frequency of the Timing Ref-
erence Clock relative to the PLL Output frequency (CLK_OUT). To minimize output jitter, the Timing Ref-
erence Clock frequency should be chosen such that f
where N is an integer.
It should be noted that there will be a jitter null at the zero point when N = 32 (not shown in
example of how to determine the range of RefClk frequencies around 12 MHz to be used in order to
achieve the lowest jitter PLL output at a frequency of 12.288 MHz is as follows:
and
XTI/REF_CLK
f
f
f
Referenced Control
RefClkDiv[1:0]
L
L
H
≤
=
=
=
=
=
=
f
RefClk
f
12.288MHz
11.919MHz
12.288MHz
12.273MHz
f
CLK_OUT
CLK_OUT
≤
f
H
.......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 32
8 MHz < RefClk <
×
×
where:
31
----- -
32
32
----- - 15kHz
32
×
×
Timing Reference Clock
0.96875
1
+
–
+
15kHz
Figure 10. Internal Timing Reference Clock Divider
15kHz
for more details.
Figure 11
Register Location
50 MHz (XTI)
58 MHz (REF_CLK)
+
15kHz
shows the effect of varying the RefClk frequency around f
Timing Reference
“AC Electrical Characteristics” on page
Clock Divider
RefClkDiv[1:0]
÷
÷
÷
1
2
4
Figure 11. REF_CLK Frequency vs. a Fixed CLK_OUT
8 MHz < SysClk < 14 MHz
180
160
140
120
100
80
60
40
20
RefClk
-80
Reference Clock
Internal Timing
-60
is at least +/-15 kHz from f
Normalized REF__CLK Frequency (kHz)
-40
-15 kHz
-20
f
CLK__OUT
0
8.
Synthesizer
*32/N
Frequency
Fractional-N
20
+15 kHz
N
“AC Electrical Char-
40
CS2000-CP
CLK__OUT Jitter
60
CLK_OUT
Figure
CLK_OUT
80
DS761F2
PLL Output
11). An
*N/32.
*N/32