CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 16

• Manufacturer Part Number: CS2000CP-CZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1748; CS2000CP-CZZ

16
Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 2
to 1048 ms) after CLK_IN is removed (see
have an effective change in period as the clock source is removed, otherwise the PLL will interpret this as
a change in frequency causing clock skipping and the 2
PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 2
pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See
Output” on page
time listed in the
output will resume.
If it is expected that CLK_IN will be removed and then reapplied within 2
t
Figure
without an indication of an unlock condition.
CS
ClkSkipEn=0 or 1
ClkOutUnl=0
ClkSkipEn=0 or 1
ClkOutUnl=0
, the ClkSkipEn bit should be disabled. If it is not disabled, the device will behave as shown in
14; note that the lower figure shows that the PLL output frequency may change and be incorrect
PLL_OUT
UNLOCK
PLL_OUT
UNLOCK
CLK_IN
CLK_IN
23. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified
“AC Electrical Characteristics” on page 8
Figure 14. CLK_IN removed for < 2
Figure 13. CLK_IN removed for > 2
ClkSkipEn= 1
ClkOutUnl= 0 or 1
t
CS
2
23
SysClk cycles
Lock Time
PLL_OUT
UNLOCK
2
CLK_IN
23
Lock Time
SysClk cycles
Figure
13). This is true as long as CLK_IN does not glitch or
t
CS
ClkSkipEn=0 or 1
ClkOutUnl=1
= invalid clocks
ClkSkipEn=0 or 1
ClkOutUnl=1
23
23
SysClk cycle time-out to be bypassed and the
Lock Time
SysClk cycles but > t
after which lock will be acquired and the PLL
23
2
23
SysClk cycles
SysClk cycles
PLL_OUT
UNLOCK
PLL_OUT
UNLOCK
CLK_IN
CLK_IN
23
SysClk cycles but later than
23
CS
SysClk cycles (466 ms
= invalid clocks
t
CS
= invalid clocks
2
23
SysClk cycles
CS2000-CP
Lock Time
23
SysClk cycles
2
23
Lock Time
“PLL Clock
SysClk cycles
DS761F2