CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 15

• Manufacturer Part Number: CS2000CP-CZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1748; CS2000CP-CZZ

DS761F2
5.1.2
5.1.3
5.2
5.2.1
Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used in Hybrid PLL Mode by the Digital PLL and Fractional-
N Logic block to dynamically generate a fractional-N value for the Frequency Synthesizer (see
alog-Digital PLL” on page
Fractional-N logic block then translates the desired ratio based off of CLK_IN to one based off of the internal
timing reference clock (SysClk). This allows the low-jitter timing reference clock to be used as the clock
which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference
clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the
acteristics” on page
Crystal Connections (XTI and XTO)
An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode par-
allel resonant crystal must be connected between the XTI and XTO pins as shown in
nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer
to the
External Reference Clock (REF_CLK)
For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the
reference clock source and XTO should be left unconnected or pulled low through a 47 kΩ resistor to
GND.
CLK_IN Skipping Mode
CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses
for up to
skipping mode can only be used when the CLK_IN frequency is below
within
“AC Electrical Characteristics” on page 8
20
20
ms of being removed. The ClkSkipEn bit enables this function.
Figure 12. External Component Requirements for Crystal Circuit
ms (t
CS
8.
) at a time (see
13). The Digital PLL first compares the CLK_IN frequency to the PLL output. The
40 pF
XTI
“AC Electrical Characteristics” on page 8
for the allowed crystal frequency range.
XTO
40 pF
80
kHz and CLK_IN is reapplied
for specifications). CLK_IN
Figure
“AC Electrical Char-
CS2000-CP
12. As shown,
“Hybrid An-
15