CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 30

• Manufacturer Part Number: CS2000CP-CZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1748; CS2000CP-CZZ

30
8.3.4
8.4
8.4.1
8.4.2
8.5
8.5.1
Reserved
Reserved
7
7
Device Configuration 2 (Address 04h)
Global Configuration (Address 05h)
Enable Device Configuration Registers 1 (EnDevCfg1)
This bit, in conjunction with EnDevCfg2, configures the device for control port mode. These EnDevCfg
bits can be set in any order and at any time during the control port access sequence, however they must
both be set before normal operation can occur.
Note:
page
Lock Clock Ratio (LockClk[1:0])
Selects one of the four stored User Defined Ratios for use in the dynamic ratio based Hybrid PLL Mode.
Fractional-N Source for Frequency Synthesizer (FracNSrc)
Selects static or dynamic ratio mode when auto clock switching is disabled.
Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h)
but keeps them from taking effect until this bit is cleared.
EnDevCfg1
0
1
Application:
LockClk[1:0]
00
01
10
11
Application:
FracNSrc
0
1
Application:
FREEZE
0
1
Device Configuration Freeze (Freeze)
24.
Reserved
Reserved
EnDevCfg2 must also be set to enable control port mode. See
6
6
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 24
CLK_IN Ratio Selection
Ratio 0.
Ratio 1.
Ratio 2.
Ratio 3.
Section 5.3.2 on page 19
Fractional-N Source Selection
Static Ratio directly from R
Dynamic Ratio from Digital PLL for Hybrid PLL Mode
“Fractional-N Source Selection” on page 21
Device Control and Configuration Registers
Register changes take effect immediately.
Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without
the changes taking effect until after the FREEZE bit is cleared.
Reserved
Reserved
5
5
Reserved
Reserved
EFF
4
4
for Frequency Synthesizer Mode
Reserved
Freeze
3
3
Reserved
LockClk1
2
2
“SPI / I²C Control Port” on
Reserved
LockClk0
1
1
CS2000-CP
EnDevCfg2
FracNSrc
DS761F2
0
0