CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet - Page 31

• Manufacturer Part Number: CS2000CP-CZZ
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1748; CS2000CP-CZZ

DS761F2
8.5.2
8.6
8.7
8.7.1
ClkSkipEn
LSB+15
MSB-8
LSB+7
MSB
7
7
Ratio 0 - 3 (Address 06h - 15h)
These registers contain the User Defined Ratios as shown in the
page
Frequency Ratio Configuration” on page 19
details.
Function Configuration 1 (Address 16h)
Enable Device Configuration Registers 2 (EnDevCfg2)
This bit, in conjunction with EnDevCfg1, configures the device for control port mode. These EnDevCfg
bits can be set in any order and at any time during the control port access sequence, however they must
both be set before normal operation can occur.
Note:
page
Clock Skip Enable (ClkSkipEn)
This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the
CLK_IN has missing pulses.
Note:
EnDevCfg2
0
1
Application:
ClkSkipEn
0
1
Application:
27. Each group of 4 registers forms a single 32-bit ratio value as shown above. See
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24.
AuxLockCfg
EnDevCfg1 must also be set to enable control port mode. See
f
CLK_IN
6
6
must be < 80 kHz and re-applied within
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 24
PLL Clock Skipping Mode
Disabled.
Enabled.
“CLK_IN Skipping Mode” on page 15
Reserved
5
5
RefClkDiv1
4
4
and
“Calculating the User Defined Ratio” on page 34
RefClkDiv0
3
3
20
ms to use this feature.
Reserved
“Register Quick Reference” section on
2
2
“SPI / I²C Control Port” on
Reserved
1
1
CS2000-CP
“Output to Input
Reserved
MSB-15
MSB-7
LSB+8
LSB
for more
0
0
31