ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 56

• Manufacturer Part Number: ADUC7032BSTZ-8L-RL
• Description: IC,Battery Management,QFP,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8L-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

ADuC7032-8L
For example, with the chop bit ADCFLT[15] set to 1, increasing
the SF value (ADCFLT[6:0]) to 0x1F (31 decimal) and selecting
an AF value (ADCFLT[13:8]) of 0x16 (22 decimal) results in an
ADC throughput of 10 Hz. The frequency response in this case
is shown in Figure 23.
Changing SF to 0x1D and setting AF to 0x3F, again with the
chop bit enabled, configures the ADC into its minimum
throughput rate in normal mode of 4 Hz. The digital filter
frequency response with this configuration is shown in Figure 24.
Table 44. Common ADCFLT Configurations
ADC Mode
Normal
Low Power
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
Figure 23. Typical Digital Filter Response at f
0
0
Figure 24. Typical Digital Filter Response at f
20
40
SF
0x1D
0x1F
0x07
0x07
0x03
0x00
0x10
0x10
0x1F
60
(ADCFLT = 0xBF1D)
(ADCFLT = 0x961F)
20
FREQUENCY (kHz)
FREQUENCY (kHz)
80
100
120
AF
0x3F
0x16
0x00
0x00
0x00
0x00
0x03
0x09
0x3D
40
140
ADC
ADC
160
= 10 Hz
= 4 Hz
180
Other Configuration
Chop on
Chop on
None
Sinc3 modify
Running average
Running average
Chop on
Chop on
Chop on
200
6
0
Rev.0 | Page 56 of 116
In ADC low power mode, the ADC Σ-Δ modulator clock is no
longer driven at 512 kHz but is driven directly from the on-chip
low power (131 kHz) oscillator. Subsequently, for the same
ADCFLT configurations in normal mode, all filter values should
be scaled by a factor of approximately 4. This means that it is
possible to configure the ADC for 1 Hz throughput in low
power mode. The filter frequency response for this
configuration is shown in Figure 25.
In general, it is possible to program different values of SF and
AF in the ADCFLT register and achieve the same ADC update
rate. In practical terms, the trade-off with any value of ADCFLT
is frequency response vs. ADC noise. For optimum filter response
and ADC noise when using combinations of SF and AF, first
choose an SF in the range of 16 to 40 (decimal) or 0x10 to 0x28.
Then increase the AF value to achieve the required ADC
throughput.
Table 44 shows some common ADCFLT configurations.
Figure 25. Typical Digital Filter Response at f
–100
ADCFLT
0xBF1D
0x961F
0x0007
0x0087
0x4003
0x4000
0x8310
0x8910
0xBD1F
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
2
4
6
FREQUENCY (kHz)
8
f
4 Hz
10 Hz
1 kHz
1 kHz
2 kHz
8 kHz
20 Hz
10 Hz
1 Hz
ADC
10
12
ADC
= 1 Hz (ADCFLT = 0xBD1F)
14
t
0.5 sec
0.2 sec
3 ms
3 ms
2 ms
0.5 ms
100 ms
200 ms
2 sec
SETTLE
16
18
2
0