AD8191AASTZ Analog Devices Inc, AD8191AASTZ Datasheet - Page 25

• Manufacturer Part Number: AD8191AASTZ
• Description: IC,Telecom Switching Circuit,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD8191AASTZ

• Function: Switch
• Circuit: 1 x 4:1
• On-state Resistance: 100 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ground Current Return
In some applications, it can be necessary to invert the output
pin order of the AD8191A, which requires a designer to route
the TMDS traces on multiple layers of the PCB. When routing
differential pairs on multiple layers, it is also necessary to
reroute the corresponding reference plane to provide one
continuous ground current return path for the differential
signals. Standard plated through-hole vias are acceptable for
both the TMDS traces and the reference plane. An example of
this is illustrated in Figure 32.
Auxiliary Control Signals
There are four single-ended control signals associated with each
source or sink in an HDMI/DVI application: hot plug detect
(HPD), consumer electronics control (CEC), and two display
data channel (DDC) lines. The two signals on the DDC bus are
SDA and SCL (serial data and serial clock, respectively). These
four signals can be switched through the auxiliary bus of the
AD8191A and do not need to be routed with the same strict
considerations as the high speed TMDS signals.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the AD8191A is being used.
For example, the maximum speed of signals present on the
auxiliary lines is 100 kHz I
any layout that enables 100 kHz I
bus should suffice. The HDMI 1.2a specification, however,
places a strict 50 pF limit on the amount of capacitance that can
be measured on either SDA or SCL at the HDMI input connector.
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR
(REFERENCE PLANE)
PCB DIELECTRIC
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
Figure 32. Example Routing of Reference Plane
2
C data on the DDC lines; therefore,
KEEP REFERENCE PLANE
ADJACENT TO SIGNAL ON ALL
LAYERS TO PROVIDE CONTINUOUS
GROUND CURRENT RETURN PATH.
THROUGH-HOLE VIAS
2
C to be passed over the DDC
Rev. 0 | Page 25 of 28
This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the AD8191A, or an
equivalent receiver. There is a similar limit of 100 pF of input
capacitance for the CEC line.
The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, the length of the CEC and DDC lines on the PCB
should be made as short as possible. Additionally, if there is a
reference plane in the layer adjacent to the auxiliary traces in
the PCB stackup, relieving or clearing out this reference plane
directly under the auxiliary traces significantly decreases the
amount of parasitic trace capacitance. An example of the board
stackup is shown in Figure 33.
HPD is a dc signal presented by a sink to a source to indicate
that the source EDID is available for reading. The placement of
this signal is not critical, but it should be routed as directly as
possible.
When the AD8191A is powered up, one set of the auxiliary
inputs is passively routed to the outputs. In this state, the
AD8191A looks like a 100 Ω resistor between the selected
auxiliary inputs and the corresponding outputs, as illustrated in
Figure 27. The AD8191A does not buffer the auxiliary signals;
therefore, the input traces, output traces, and the connection
through the AD8191A all must be considered when designing a
PCB to meet HDMI/DVI specifications. The unselected auxiliary
inputs of the AD8191A are placed into a high impedance mode
when the device is powered up. To ensure that all of the
auxiliary inputs of the AD8191A are in a high impedance mode
when the device is powered off, it is necessary to power the
AMUXVCC supply as illustrated in Figure 28.
In contrast to the auxiliary signals, the AD8191A buffers the
TMDS signals, allowing a PCB designer to layout the TMDS
inputs independently of the outputs.
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
Figure 33. Example Board Stackup
3W
RELIEVED UNDERNEATH
REFERENCE LAYER
MICROSTRIP
W
3W
AD8191A