AD8191-EVAL Analog Devices Inc, AD8191-EVAL Datasheet

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... Flexible channel bundling modes (for both the TMDS channels and the auxiliary signals) allow the AD8191 to be configured as a 4:1 single HDMI/DVI link switch, a dual 8:1 switch single 16:1 switch. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable ...

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... AD8191 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Typical Application........................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Maximum Power Dissipation ..................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 13 Introduction ................................................................................ 13 Input Channels............................................................................ 13 Output Channels ........................................................................ 13 High Speed (TMDS) Switching Modes ...

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... Outputs enabled, maximum pre-emphasis 4 Input termination on Output termination on, no pre-emphasis Output termination on, maximum pre-emphasis Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis High speed switching register: HS_CH All other configuration registers Rev Page AD8191 Min Typ Max Unit 1.65 Gbps − (p-p) 2 ...

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... Differential interpair skew is measured between the TMDS pairs of a single link. 2 AD8191 output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.2a. 3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.2a. ...

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... LQFP 2.2 W AVCC − 1.4 V < V < IN MAXIMUM POWER DISSIPATION AVCC + 0.6 V The maximum power that can be safely dissipated by the AD8191 2 limited by the associated rise in junction temperature. The DVEE − 0.3 V < V < IN AMUXVCC + 0.6 V maximum safe junction temperature for plastic encapsulated DVEE − ...

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... IP_B1 7, 19, 57, 69 VTTI 8 IN_B2 9 IP_B2 11 IN_B3 12 IP_B3 14 IN_A0 15 IP_A0 AD8191 TOP VIEW (Not to Scale) Figure 3. Pin Configuration 1 Type Description Power Positive Analog Supply. 3.3 V nominal High Speed Input Complement High Speed Input. Power Negative Analog Supply nominal High Speed Input Complement. ...

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... High Speed Input Complement High Speed Input High Speed Input Complement High Speed Input High Speed Input Complement High Speed Input. Control High Speed Output Enable Parallel Interface. Control High Speed Equalization Selection Parallel Interface. LS I/O Low Speed Input/Output. Rev Page AD8191 ...

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... AD8191 Pin No. Mnemonic 79 AUX_D2 80 AUX_D1 81 AUX_D0 82 AMUXVCC 83 AUX_C3 84 AUX_C2 85 AUX_C1 86 AUX_C0 87 AUX_COM3 88 AUX_COM2 89 AUX_COM1 90 AUX_COM0 91 AUX_B3 92 AUX_B2 93 AUX_B1 94 AUX_B0 96 AUX_A3 97 AUX_A2 98 AUX_A1 99 AUX_A0 100 PP_OTO high speed low speed input output. 1 Type Description LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. ...

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... Figure 4. Test Circuit Diagram for RX Eye Diagram Figure 7. RX Eye Diagram at TP3 (Cable = 2 meters, 30 AWG) Figure 8. RX Eye Diagram at TP3 (Cable = 20 meters, 24 AWG) Rev Page − 1, data rate = 1.65 Gbps, unless AD8191 SERIAL DATA EVALUATION ANALYZER BOARD SMA COAX CABLE TP2 TP3 0.125UI/DIV AT 1.65Gbps 0.125UI/DIV AT 1.65Gbps AD8191 ...

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... TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 2 otherwise noted. REFERENCE EYE DIAGRAM AT TP1 0.125UI/DIV AT 1.65Gbps Figure 10. TX Eye Diagram at TP2 0.125UI/DIV AT 1.65Gbps Figure 11. TX Eye Diagram at TP2 AD8191 DIGITAL EVALUATION PATTERN BOARD GENERATOR SMA COAX CABLE ...

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... DATA RATE (Gbps) Figure 18. Eye Height vs. Data Rate 800 700 600 500 400 300 200 100 0 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) Figure 19. Eye Height vs. Supply Voltage AD8191 20 25 1.4 1.6 1.8 3.5 3.6 ...

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... AD8191 T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input A swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 2 otherwise noted (p- (rms 0.2 0.4 0.6 0.8 1.0 1.2 DIFFERENTIAL INPUT SWING (mV) Figure 20 ...

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... THEORY OF OPERATION INTRODUCTION The primary function of the AD8191 is to switch one of four (HDMI or DVI) single-link sources to one output. Each HDMI/DVI link consists of four differential, high speed channels and four auxiliary single-ended, low speed control signals. The high speed channels include a data-word clock and three transition minimized differential signaling (TMDS) data channels running at 10× ...

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... DDC bus, regardless of the state of the AD8191 and any downstream circuit. For this configuration, the auxiliary inputs of the powered down AD8191 need high impedance state to avoid pulling down on the DDC lines and preventing these other devices from using the bus. ...

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... Table 14. This mode is only accessible through the serial control interface. Single Switching Mode In this mode the AD8191 behaves as a single 16:1 TMDS channel multiplexer; a single channel, out of a possible 16, is routed to all of the outputs. The user selects which input channel is routed to the outputs by programming the AUX_CH bits of the auxiliary device modes register in accordance with the switch mapping listed in Table 15 ...

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... I2C_SDA line low). 2. Send the AD8191 part address (seven bits). The upper four bits of the AD8191 part address are the static value [1001] and the three LSBs are set by Input Pin I2C_ADDR2, Input Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB). This transfer should be MSB first ...

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... I2C_SCL line high and pulling the I2C_SDA line low. 8. Resend the AD8191 part address (seven bits) from Step 2. The upper four bits of the AD8191 part address are the static value [1001] and the three LSBs are set by the Input Pin I2C_ADDR2, I2C_ADDR1 and Input Pin I2C_ADDR0 (LSB) ...

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... Table 1. Setting these pins updates the parallel control interface registers, as listed in Table 24. Following a reset, the AD8191 can be controlled through the parallel control interface until the first serial control event occurs. As soon as any serial control ...

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... The serial interface configuration registers can be read and written using the I The least significant bits of the AD8191 I 3.3 V (Logic (Logic 0). As soon as the serial control interface is used, the parallel control interface is disabled until the AD8191 is reset as described in the Serial Control Interface section. ...

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... AD8191 Table 9. Dual Mode, 2× [8:1], High Speed Switch Mapping HS_CH[3:0] O[3:2] O[1:0] Description X000 A1 A0 The A0 and A1 high speed channels switched to output X001 A3 A2 The A2 and A3 high speed channels switched to output X010 B1 B0 The B0 and B1 high speed channels switched to output ...

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... The B2 and D2 auxiliary 1111 AUX_D3 channels switched to output The B3 and D3 auxiliary channels switched to output Rev Page AD8191 Description Auxiliary Channel A0 switched to output Auxiliary Channel A1 switched to output Auxiliary Channel A2 switched to output Auxiliary Channel A3 switched to output Auxiliary Channel B0 switched to output Auxiliary Channel B1 switched to output ...

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... AD8191 RECEIVER SETTINGS REGISTER RX_TO: High Speed (TMDS) Channels Input Termination On/Off Select Bit Table 16. RX_TO Description RX_TO Description 0 Input termination off 1 Input termination on (can be pulsed on and off according to settings in the input termination pulse register) INPUT TERMINATION PULSE REGISTER 1 AND REGISTER 2 ...

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... PP_CH[1:0]: Auxiliary Switch Source Select Bus Table 27. Quad Auxiliary Switch Mode Mapping PP_CH[1: Rev Page AD8191 Bit 1 Bit 0 High speed source select PP_CH[1] PP_CH[0] Auxiliary switch source select PP_CH[1] PP_CH[0] Input term. on/off ...

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... AD8191 RECEIVER SETTINGS REGISTER High speed (TMDS) channels input termination is fixed to on when using the parallel interface. INPUT TERMINATION PULSE REGISTER 1 AND REGISTER 2 High speed input (TMDS) channels pulse-on-source switching fixed to off when using the parallel interface. RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2 ...

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... APPLICATION INFORMATION Figure 31. Layout of the TMDS Traces on the AD8191 Evaluation Board (Only Top Signal Routing Layer is Shown) The AD8191 is an HDMI/DVI switch featuring equalized TMDS inputs and pre-emphasized TMDS outputs in- tended for use as a 4:1 switch in systems with long cable runs on both the input and/or the output, and is fully HDMI 1 ...

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... PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the AD8191, all four high speed signals should be routed on a PCB in accordance with the same RF layout guidelines. ...

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... SDA and SCL (serial data and serial clock, respectively). These four signals can be switched through the auxiliary bus of the AD8191 and do not need to be routed with the same strict considerations as the high speed TMDS signals. In general sufficient to route each auxiliary signal as a single-ended trace ...

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... When the AD8191 is powered up, one set of the auxiliary in- puts is passively routed to the outputs. In this state, the AD8191 looks like a 100 Ω resistor between the selected auxiliary inputs and the corresponding outputs as illustrated in Figure 27. The ...

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... In applications where the AD8191 is powered by a single 3.3 V supply recommended to use two reference supply planes and bypass the 3.3 V reference plane to the ground reference plane with one 220 pF, one 1000 pF, two 0.01 μF, and one 4.7 μF capacitors. The capacitors should via down directly to the supply planes and be placed within a few centimeters of the AD8191 ...

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... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 AD8191ASTZ −40°C to +85°C 1 AD8191ASTZ-RL −40°C to +85°C AD8191-EVAL Pb-free part. 16.20 16.00 SQ 1.60 MAX 15.80 0.75 100 1 0.60 0.45 PIN 1 TOP VIEW (PINS DOWN) 0.20 0.09 7° ...

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... NOTES Rev Page AD8191 ...

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... AD8191 NOTES Purchase of licensed 2 components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...