AD8191AASTZ Analog Devices Inc, AD8191AASTZ Datasheet - Page 15

• Manufacturer Part Number: AD8191AASTZ
• Description: IC,Telecom Switching Circuit,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD8191AASTZ

• Function: Switch
• Circuit: 1 x 4:1
• On-state Resistance: 100 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL CONTROL INTERFACE
RESET
On initial power-up, or at any point in operation, the AD8191A
register set can be restored to preprogrammed default values by
pulling the RESET pin low in accordance with the specifications
in Table 1. During normal operation, however, the RESET pin
must be pulled up to 3.3 V. Following a reset, the preprogrammed
default values of the AD8191A register set correspond to the
state of the parallel interface configuration registers, as listed in
Table 18. The AD8191A can be controlled through the parallel
control interface until the first serial control event occurs.
As soon as any serial control event occurs, the serial
programming values, corresponding to the state of the serial
interface configuration registers (see Table 5), override any
prior parallel programming values, and the parallel control
interface is disabled until the part is subsequently reset.
WRITE PROCEDURE
To write data to the AD8191A register set, an I
as a microcontroller) needs to send the appropriate control
signals to the AD8191A slave device. The signals are controlled
by the I
the procedure, see Figure 29. The steps for a write procedure are
as follows:
1.
2.
3.
Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).
Send the AD8191A part address (seven bits). The upper
four bits of the AD8191A part address are the static value
[1001] and the three LSBs are set by Input Pin I2C_ADDR2,
Input Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB).
This transfer should be MSB first.
Send the write indicator bit (0).
GENERAL CASE
2
C master, unless otherwise specified. For a diagram of
EXAMPLE
I2C_SDA
I2C_SDA
I2C_SCL
*THE SWITCHING/UPDATE DELAY BEGINS AT THE FALLING EDGE OF THE
LAST DATA BIT; FOR EXAMPLE, THE FALLING EDGE JUST BEFORE STEP 8.
START
1
2
FIXED PART
ADDR
ADDR
2
C master (such
R/W
3
ACK
Figure 29. I
4
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5
2
REGISTER ADDR
C Write Diagram
4.
5.
6.
7.
8.
9.
Wait for the AD8191A to acknowledge the request.
Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
Wait for the AD8191A to acknowledge the request.
Send the data (eight bits) to be written to the register
whose address was set in Step 5. This transfer should be
MSB first.
Wait for the AD8191A to acknowledge the request.
Perform one of the following:
9a. Send a stop condition (while holding the I2C_SCL
9b. Send a repeated start condition (while holding the
9c. Send a repeated start condition (while holding the
9d. Send a repeated start condition (while holding the
line high, pull the I2C_SDA line high) and release
control of the bus to end the transaction (shown in
Figure 29).
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 in this procedure to perform
another write.
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of the read procedure (in the
Read Procedure section) to perform a read from
another address.
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 8 of the read procedure (in the
Read Procedure section) to perform a read from the
same address set in Step 5.
ACK
6
7
DATA
*
ACK
8
AD8191A
STOP
9