AD8191AASTZ Analog Devices Inc, AD8191AASTZ Datasheet - Page 20

• Manufacturer Part Number: AD8191AASTZ
• Description: IC,Telecom Switching Circuit,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD8191AASTZ

• Function: Switch
• Circuit: 1 x 4:1
• On-state Resistance: 100 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8191A
PARALLEL INTERFACE CONFIGURATION REGISTERS
The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and
PP_OCL pins. This interface is only accessible after the part is reset and before any registers are accessed using the serial control interface.
The state of each pin is set by tying it to 3.3 V (Logic 1) or 0 V (Logic 0).
Table 18. Parallel Interface Register Map
Name
High Speed
Device Modes
Auxiliary
Device Modes
Receiver
Settings
Input
Termination
Pulse Register 1
Input
Termination
Pulse Register 2
Receive
Equalizer
Register 1
Receive
Equalizer
Register 2
Transmitter
Settings
HIGH SPEED DEVICE MODES REGISTER
PP_EN: High Speed (TMDS) Channels Enable Bit
Table 19. PP_EN Description
PP_EN
0
1
PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus
Table 20. High Speed Switch Mapping
PP_CH[1:0]
00
01
10
11
Description
High speed channels off, low power/standby mode
High speed channels on
O[3:0]
A[3:0]
B[3:0]
C[3:0]
D[3:0]
Bit 7
0
0
PP_EQ
PP_EQ
Description
High Speed Source A switched to output
High Speed Source B switched to output
High Speed Source C switched to output
High Speed Source D switched to output
Bit 6
High speed
channel
enable
PP_EN
Auxiliary
switch enable
1
0
0
PP_EQ
PP_EQ
Source C and Source D input termination select (termination always off )
Source A and Source B input termination select (termination always off )
Bit 5
0
0
0
0
PP_EQ
PP_EQ
Source C and Source D input equalization level select
Source A and Source B input equalization level select
Bit 4
0
0
0
0
PP_EQ
PP_EQ
Rev. 0 | Page 20 of 28
Bit 3
0
0
0
0
PP_EQ
PP_EQ
Output pre-emphasis
PP_PE[1]
AUXILIARY DEVICE MODES REGISTER
PP_CH[1:0]: Auxiliary Switch Source Select Bus
Table 21. Auxiliary Switch Mapping
PP_CH[1:0]
00
01
10
11
RECEIVER SETTINGS REGISTER
High speed (TMDS) channels input termination is fixed to on
when using the parallel interface.
level select
Bit 2
0
0
0
0
PP_EQ
PP_EQ
PP_PE[0]
AUX_COM[3:0]
AUX_A[3:0]
AUX_B[3:0]0
AUX_C[3:0]
AUX_D[3:0]
Bit 1
PP_CH[1]
PP_CH[1]
0
0
PP_EQ
PP_EQ
Output
termination
on/off select
PP_OTO
Auxiliary switch source select
High speed source select
Description
Auxiliary Source A switched to
output
Auxiliary Source B switched to
output
Auxiliary Source C switched to
output
Auxiliary Source D switched to
output
Bit 0
PP_OCL
PP_CH[0]
PP_CH[0]
Input termination
on/off select
(termination always on)
1
0
0
PP_EQ
PP_EQ
Output current level
select