5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 39

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 2: MAX V Architecture
I/O Structure
Figure 2–19. IOE Structure for MAX V Devices
Notes to
(1) Available only in I/O bank 3 of 5M1270Z and 5M2210Z devices.
(2) The programmable pull-up resistor is active during power-up, in-system programming (ISP), and if the device is unprogrammed.
December 2010 Altera Corporation
Figure
Fast I/O Connection
Data_in
2–19:
Fast_out
A dedicated fast I/O connection from the adjacent LAB to the IOEs within an I/O
block provides faster output delays for clock-to-output and t
This connection exists for data output signals, not output enable signals or input
signals.
Data_out
Figure
OE
2–20,
Figure
Drive Strength Control
Programmable
Input Delay
Open-Drain Output
DEV_OE
2–21, and
Slew Control
Optional Schmitt
Trigger Input
Figure 2–22
Optional
PCI Clamp (1)
V
CCIO
V
illustrate the fast I/O connection.
CCIO
I/O Pin
Programmable
Pull-Up (2)
PD
Optional Bus-Hold
Circuit
propagation delays.
MAX V Device Handbook
2–27