5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 101

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 6: JTAG and In-System Programmability in MAX V Devices
In-System Programmability
Table 6–4. Family Programming Times for MAX V Devices
December 2010 Altera Corporation
Erase + Program (1 MHz)
Erase + Program (10 MHz)
Verify (1 MHz)
Verify (10 MHz)
Complete Program Cycle (1 MHz)
Complete Program Cycle (10 MHz)
Notes to
(1) Not applicable to T144 package of the 5M240Z device.
(2) Only applicable to T144 package of the 5M240Z device.
(3) Not applicable to F324 package of the 5M1270Z device.
(4) Only applicable to F324 package of the 5M1270Z device.
Table
User Flash Memory Programming
In-System Programming Clamp
Description
6–4:
f
A stand-alone verification of a programmed pattern involves only steps 1, 2, 5, and 6.
These steps are automatically executed by third-party programmers, the Quartus II
software, or the Jam STAPL and Jam Byte-Code Players.
Table 6–4
execute the algorithm vectors in hardware. Because of data processing and data
transfer limitations, software-based programming tools used with download cables
are slightly slower.
The Quartus II software (with the use of .pof, .jam, or .jbc files) supports
programming of the UFM block independent of the logic array design pattern stored
in the CFM block. This allows updating or reading UFM contents through ISP without
altering the current logic array design, or vice versa. By default, these programming
files and methods program the entire flash memory contents, which includes the CFM
block and UFM contents. The stand-alone embedded Jam STAPL Player and Jam
Byte-Code Player provide action commands for programming or reading the entire
flash memory (UFM and CFM together) or each independently.
For more information, refer to
Device
By default, the IEEE 1532 instruction used for entering ISP automatically tri-states all
I/O pins with weak pull-up resistors for the duration of the ISP sequence. However,
some systems may require certain pins on MAX V devices to maintain a specific DC
logic level during an in-field update. For these systems, you can use the optional in-
system programming clamp instruction in the MAX V circuitry to control I/O
Programming.
lists the programming times for MAX V devices with in-circuit testers to
5M240Z
5M160Z/
5M40Z/
5M80Z/
1.72
1.65
0.09
0.01
1.81
1.66
(1)
5M240Z
2.16
1.99
0.17
0.02
2.33
2.01
(2)
AN 425: Using the Command-Line Jam STAPL Solution for
5M570Z
2.16
1.99
0.17
0.02
2.33
2.01
5M1270Z
2.90
2.58
0.30
0.03
3.20
2.61
(3)
5M1270Z
3.92
3.40
0.49
0.05
4.41
3.45
MAX V Device Handbook
(4)
5M2210Z
3.92
3.40
0.05
0.49
4.41
3.45
6–7
Unit
sec
sec
sec
sec
sec
sec