5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 155

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
IEEE Std. 1149.1 BST Operation Control
Figure 8–8. IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode
December 2010 Altera Corporation
Figure 8–8
SAMPLE/PRELOAD instruction code shifts in through the TDI pin. The TAP controller
advances to the CAPTURE_DR state and then to the SHIFT_DR state, where it remains if
TMS is held low. The data shifted out of the TDO pin consists of the data that was
present in the capture registers after the capture phase. New test data shifted into the
TDI pin appears at the TDO pin after being clocked through the entire boundary-scan
register.
OUTJ
OUTJ
OEJ
OEJ
INJ
INJ
SHIFT
SHIFT
SDI
SDI
shows the capture, shift, and update phases of SAMPLE/PRELOAD mode.
0
1
0
1
0
1
0
1
0
1
0
1
CLOCK
CLOCK
D
D
D
D
D
D
Output
Output
Input
Input
OE
OE
Q
Q
Q
Q
Q
Q
(Shift and Update Phase)
SDO
SDO
Capture
Registers
Capture
Registers
(Capture Phase)
UPDATE
UPDATE
D
D
D
D
Output
Output
OE
OE
Q
Q
Q
Q
Update
Registers
Update
Registers
HIGHZ
HIGHZ
0
1
0
1
MODE
MODE
0
1
0
1
0
1
0
1
Global Signals
Global Signals
PIN_IN
PIN_OE
PIN_OUT
PIN_IN
PIN_OE
PIN_OUT
Output
Buffer
Output
Buffer
Pin
Pin
MAX V Device Handbook
8–9