5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet
5M80ZT100C5N
Specifications of 5M80ZT100C5N
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5M80ZT100C5N Summary of contents
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... This section provides a complete overview of all features relating to the MAX device family. This section includes the following chapters: ■ Chapter 1, MAX V Device Family Overview ■ Chapter 2, MAX V Architecture ■ Chapter 3, DC and Switching Characteristics for MAX V Devices May 2011 Altera Corporation Section I. MAX V Device Core MAX V Device Handbook ® V ...
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... I–2 MAX V Device Handbook Section I: MAX V Device Core May 2011 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... CCINT ) are 1.2 V, 1.5 V, 1.8 V, 2.5 V, CCIO chapter. May 2011 Altera Corporation ...
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... For more information about the In-System Sources and Probes Editor, refer to the Design Debugging Using In-System Sources and Probes Handbook. Device Pin-Outs f For more information, refer to the May 2011 Altera Corporation (Note 1) 68-Pin 100-Pin 100-Pin MBGA TQFP MBGA — ...
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... Table 1–3. ■ Updated “Feature Summary” section. Initial release. Chapter 1: MAX V Device Family Overview Ordering Information N Optional Suffix Indicates specific device options or shipment method N: Lead-free packaging ° ° ° ° 100 C) J ° ° 125 C) J May 2011 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... MAX V Device Handbook IOE IOE IOE IOE Logic Logic Element Element Logic Logic Element Element Logic Logic Element Element Logic Logic Element Element MultiTrack Interconnect chapter. Chapter 2: MAX V Architecture Functional Description IOE Logic Array BLock (LAB) Hot Socketing December 2010 Altera Corporation ...
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... Not applicable to T144 package of the 5M240Z device. (3) Only applicable to T144 package of the 5M240Z device. (4) Not applicable to F324 package of the 5M1270Z device. (5) Only applicable to F324 package of the 5M1270Z device. December 2010 Altera Corporation LAB Rows LAB Columns Long LAB Rows Short LAB Rows (Width) ...
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... LAB. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the LUT output from one LE to the MAX V Device Handbook (Note 1) UFM Block CFM Block Chapter 2: MAX V Architecture Logic Array Blocks Logic Array Blocks 2 GCLK Inputs December 2010 Altera Corporation ...
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... LAB or IOE DirectLink interconnect to adjacent LAB or IOE Logic Element Note to Figure 2–3: (1) Only from LABs adjacent to IOEs. December 2010 Altera Corporation ® II software places associated logic within an LAB or Figure 2–3 shows the MAX V LAB. Row Interconnect LE0 LE1 LE2 LE3 LE4 ...
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... DirectLink connection. DirectLink interconnect to left Local Interconnect Logic Element Chapter 2: MAX V Architecture Logic Array Blocks DirectLink interconnect from right LAB or IOE output LE0 LE1 LE2 LE3 LE4 LE5 DirectLink LE6 interconnect to right LE7 LE8 LE9 LAB December 2010 Altera Corporation ...
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... LAB Column Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local labclk1 Interconnect December 2010 Altera Corporation Figure 2–5 shows the LAB control signal labclkena1 labclkena2 syncload labclk2 asyncload or labpre 2–7 labclr2 addnsub labclr1 synclr MAX V Device Handbook ...
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... ADATA Clear Logic ENA CLRN Register Feedback Carry-Out0 Carry-Out1 LAB Carry-Out Chapter 2: MAX V Architecture Logic Elements Programmable Register LUT chain routing to next LE Row, column, and DirectLink Q routing Row, column, and DirectLink routing Local routing Register chain output December 2010 Altera Corporation ...
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... The Quartus II software, along with parameterized functions such as the library of parameterized modules (LPM) functions, automatically chooses the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. December 2010 Altera Corporation “MultiTrack Interconnect” on page MAX V Device Handbook 2–9 ...
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... LAB carry-in signal selects either the carry-in0 or Chapter 2: MAX V Architecture Logic Elements 2–7. The Quartus II Compiler aload (LAB Wide) ALD/PRE Row, column, and ADATA Q DirectLink routing D Row, column, and ENA DirectLink routing CLRN Local routing LUT chain connection Register chain output December 2010 Altera Corporation ...
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... LUT and the next portion of the carry chain. Carry-select chains can begin in any LE within an LAB. December 2010 Altera Corporation sload sclear ...
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... LE5 B6 Sum7 A7 LE6 B7 Sum8 A8 LE7 B8 Sum9 A9 LE8 B9 Sum10 A10 LE9 B10 LAB Carry-Out MAX V Device Handbook LAB Carry-In Carry-In0 Carry-In1 data1 data2 Carry-Out0 To top of adjacent LAB Chapter 2: MAX V Architecture Logic Elements LUT Sum LUT LUT LUT Carry-Out1 December 2010 Altera Corporation ...
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... FIFO synchronous R/W ■ FIFO asynchronous R/W ■ 1 port SRAM 2 port SRAM ■ 3 port SRAM ■ ■ shift registers f For more information about memory, refer to the User Guide. December 2010 Altera Corporation 2–13 Internal Memory (RAM and ROM) MAX V Device Handbook ...
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... R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 interconnects for connections from one row to another. MAX V Device Handbook shows R4 interconnect connections from an LAB. R4 interconnects Chapter 2: MAX V Architecture MultiTrack Interconnect December 2010 Altera Corporation ...
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... LE to connect directly to the register input of the next LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. shows the LUT chain and register chain interconnects. December 2010 Altera Corporation Adjacent LAB can drive onto another C4 Column Interconnects (1) LAB’ ...
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... Routing Among LEs in the LAB LE0 LUT Chain Register Chain Routing to Routing to Adjacent Adjacent LE LE's Register Input LE1 Local LE2 Interconnect LE3 LE4 LE5 LE6 LE7 LE8 LE9 Chapter 2: MAX V Architecture MultiTrack Interconnect Figure 2–12 shows the C4 December 2010 Altera Corporation ...
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... Figure 2–12. C4 Interconnect Connections Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Note to Figure 2–12: (1) Each C4 interconnect can drive either up or down four rows. December 2010 Altera Corporation (Note 1) Local Interconnect 2–17 C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows C4 Interconnect ...
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... December 2010 Altera Corporation ...
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... LAB clock signals and one LAB clear signal. Other control signal types route from the global clock network into the LAB local interconnect. For more information, refer to December 2010 Altera Corporation Figure 2–13. These four pins can also be used as GPIOs if ...
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... LAB column clocks in I/O block regions provide high fan-out output enable signals. (2) LAB column clocks drive to the UFM block. MAX V Device Handbook UFM Block (2) CFM Block Chapter 2: MAX V Architecture Global Signals LAB Column clock[3..0] 4 I/O Block Region December 2010 Altera Corporation ...
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... Program, erase, and busy signals ■ Auto-increment addressing ■ Serial interface to logic array with programmable interface Figure 2–15. UFM Block and Interface Signals December 2010 Altera Corporation shows the UFM block and interface signals. The logic array is UFM Block PROGRAM Program Erase ...
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... Figure 2–15, the dedicated circuitry within the UFM block contains an Chapter 2: MAX V Architecture User Flash Memory Block Table 2–3 lists the data Address Bits Data Width ™ Plug-In December 2010 Altera Corporation ...
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... SPI are also automatically generated in LE logic by the Quartus II software. f For more information about the UFM interface signals and the Quartus II LE-based alternate interfaces, refer to the December 2010 Altera Corporation chapter. User Flash Memory in MAX V Devices 2–23 chapter. ...
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... Figure 2–16. The interface regions for Figure CFM Block UFM Block LAB PROGRAM ERASE OSC_ENA LAB RTP_BUSY DRDin DRCLK DRSHFT ARin ARCLK LAB ARSHFT DRDout OSC BUSY Chapter 2: MAX V Architecture User Flash Memory Block 2–17. (Note 1), (2) December 2010 Altera Corporation ...
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... Figure 2–17: (1) Only applicable to the T144 package of the 5M240Z device. Core Voltage The MAX V architecture supports a 1.8-V core voltage on the V use a 1.8-V V Figure 2–18. Core Voltage Feature in MAX V Devices December 2010 Altera Corporation CFM Block RTP_BUSY BUSY OSC DRDout DRDin DRDCLK ...
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... Quartus II software automatically routes the register to guarantee zero hold time. You can set timing assignments in the Quartus II software to achieve desired I/O timing. MAX V Device Handbook Chapter 2: MAX V Architecture I/O Structure Figure 2–19 shows the MAX V December 2010 Altera Corporation ...
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... Data_out OE Notes to Figure 2–19: (1) Available only in I/O bank 3 of 5M1270Z and 5M2210Z devices. (2) The programmable pull-up resistor is active during power-up, in-system programming (ISP), and if the device is unprogrammed. December 2010 Altera Corporation 2–20, Figure 2–21, and Figure 2–22 DEV_OE Optional PCI Clamp (1) ...
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... Interconnect Direct Link from Adjacent LAB Interconnect to Adjacent LAB Chapter 2: MAX V Architecture I/O Structure (Note 1) I/O Block Local Interconnect data_out [6.. [6..0] 7 Row fast_out I/O Block [6.. Row I/O Block Contains up to LAB Column Seven IOEs clock [3..0] December 2010 Altera Corporation ...
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... I/O Standards and Banks Table 2–4 lists the I/O standards supported by MAX V devices. Table 2–4. MAX V I/O Standards (Part I/O Standard 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS December 2010 Altera Corporation Column I/O Block data_out OE fast_out [3..0] [3..0] [3.. ...
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... PCI compliant I/O is not supported in these All I/O Banks Support 3.3-V LVTTL/LVCMOS, 2.5-V LVTTL/LVCMOS, 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, 1.2-V LVCMOS (3), LVDS (4) , RSDS (5) Chapter 2: MAX V Architecture I/O Structure Output Supply Voltage (V ) CCIO (V) 3.3 2.5 2.5 (Note 1), (2) I/O Bank 2 December 2010 Altera Corporation ...
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... I/O pins. The pins TMS, TDI, TDO, and TCK support all the I/O standards shown in Table 2–4 on page 2–29 for all MAX V devices and their I/O standard support is controlled by the V setting for Bank 1. December 2010 Altera Corporation 2–4. PCI compliant I/O is supported in Bank 3. Bank 3 supports the I/O Bank 2 All I/O Banks Support 3 ...
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... PCI All Speed Grades All Speed Grades 144 TQFP 256 FBGA 324 FBGA — — — — — — — — — 49 eTx — — 49 eTx 75 eTx — 42 eTx 90 eTx 115 eTx — 83 eTx 115 eTx December 2010 Altera Corporation ...
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... I/O standard. The maximum, where the V OUT OL the I condition The programmable drive strength feature can be used simultaneously with the slew-rate control feature. December 2010 Altera Corporation Table 2–7 lists the possible settings for the I/O standards (Note 1) IOH/IOL Current Strength Setting (mA ...
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... The bus-hold circuitry is only active after the device has fully initialized. The bus-hold circuit captures the value on the pin present at the moment user mode is entered. MAX V Device Handbook Chapter 2: MAX V Architecture I/O Structure December 2010 Altera Corporation ...
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... VCCIO (V) 1.2 V 1 — — 1 — 1 — 1.8 — — — 2.5 December 2010 Altera Corporation level of the output pin’s bank. CCIO Table 2–8 summarizes MAX V MultiVolt I/O support. (Note 1) 2.5 V 3.3 V 5.0 V 1 — — — — — ...
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... V 3.3 V 5.0 V 1 (4) (5) (6) from rising above 4.0 V. Use an external diode if the I/O pin does not support the clamp I Changes Chapter 2: MAX V Architecture Document Revision History Output Signal 1.8 V 2.5 V 3 (6) (6) (6) (7) December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... MAX V device ISP and/or user flash memory (UFM) programming using JTAG or logic array is not guaranteed outside the recommended operating conditions (for example, if brown-out occurs in the system during a potential write/program sequence to the UFM, Altera recommends that you read back the UFM contents and verify it against the intended write data). ...
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... Hysteresis for Schmitt V (8) SCHMITT trigger input (9) V supply current CCINT I CCPOWERUP during power-up (10) Value of I/O pin pull-up R resistor during user PULLUP mode and ISP May 2011 Altera Corporation Block Minimum — — (Note 1) (Part Conditions Minimum = V max (2) –10 I CCIO max (2) – ...
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... Conditions Minimum — — — — — — = 1.2, 1.5, 1.8, 2.5, or 3.3 V. CCIO time. CONFIG . CCIO Operating Conditions Typical Maximum Unit — 300 µA — — settings (3.3, 2.5, 1.8, 1.5, CCIO typical value is 300 mV SCHMITT May 2011 Altera Corporation ...
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... High-level output voltage OH V Low-level output voltage OL Note to Table 3–5: (1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the MAX V Device Architecture chapter. May 2011 Altera Corporation (Note 1) MAX V Output Drive 0.0 0.5 2 ...
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... V IH Operating Conditions Maximum Unit 3.6 V 4.0 V 0.8 V — V 0.2 V Maximum Unit 2.625 V 4.0 V 0.7 V — V — V — V 0.2 V 0.4 V 0.7 V Maximum Unit 1.89 V 2.25 (2) V 0.35 × CCIO — V 0.45 V parameter I May 2011 Altera Corporation ...
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... I/O supply voltage CCIO V Differential output voltage swing OD V Output offset voltage OS Note to Table 3–12: (1) Supports emulated LVDS output using a three-resistor network (LVDS_E_3R). May 2011 Altera Corporation Conditions Minimum — 1.425 — 0.65 × V CCIO — –0.3 IOH = –2 mA (1) 0.75 × V ...
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... Operating Conditions Typical Maximum Unit 2.5 2.625 V — 600 mV 1.25 1.375 V 2.5 V 3.3 V Unit Min Max Min Max 50 — 70 — µA –50 — –70 — µA — 300 — 500 µA — –300 — –500 µA May 2011 Altera Corporation ...
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... Not applicable to the T144 package of the 5M240Z device. (3) Only applicable to the T144 package of the 5M240Z device. (4) Not applicable to the F324 package of the 5M1270Z device. (5) Only applicable to the F324 package of the 5M1270Z device. May 2011 Altera Corporation Device Temperature Range Commercial and industrial ...
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... For more information about these power analysis tools, refer to the Power Estimator for Altera CPLDs User Guide in volume 3 of the Quartus II Handbook. Timing Model and Specifications MAX V devices timing can be analyzed with the Altera Quartus of industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure MAX V devices have predictable internal delays that allow you to determine the worst-case timing of any design ...
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... LE 32-to-1 multiplexer — 16-bit XOR function — 16-bit decoder with — single address line May 2011 Altera Corporation Table 3–16 lists the status of the MAX V device timing models. Device 5M40Z 5M80Z 5M160Z 5M240Z 5M570Z 5M1270Z 5M2210Z Resources Used ...
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... Table 3–18 timing microparameters for LEs, input/output elements (IOEs), UFM blocks, and MultiTrack interconnects. f For more information about each internal timing microparameters symbol, refer to AN629: Understanding Timing in Altera Table 3–18. LE Internal Timing Microparameters for MAX V Devices (Part Symbol Parameter LE combinational look-up ...
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... Table 3–23 on page 3–15. (4) For more information about t delay adders associated with different I/O standards, drive strengths, and slew rates, refer to ZX page 3–14 and Table 3–21 on page 3–14. May 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Min Max Min Max 253 — ...
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... Min Max 6,012 — 5,743 ps 8,785 — 8,516 ps 6,012 — 5,743 ps 8,785 — 8,516 ps 10,072 — 9,803 ps 12,945 — 12,676 ps 21,185 — 20,916 ps 24,597 — 24,328 ps 34,517 — 34,248 ps 39,717 — 39,448 ps 55,800 — 55,531 ps 35 — May 2011 Altera Corporation ...
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... LVTTL / LVCMOS 3 mA — — 1.5-V LVCMOS 2 mA — 1.2-V LVCMOS 3 mA — 3.3-V PCI 20 mA — May 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Max Min Max Min 0 — 0 — –69 — –69 — 0 — ...
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... May 2011 Altera Corporation µs ...
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... Maximum delay between the OSC_ENA rising edge t OSCS to the erase/program signal rising edge Minimum delay allowed from the t erase/program signal OSCH going low to OSC_ENA signal going low May 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Min Max Min Max 0 — 0 — ...
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... Table 3–24. 9 Address Bits t AH ACLK t ADH 16 Data Bits t DCLK t DSS t DCO ADH 16 Data Bits t t DCLK DSS t DDH t DDS Timing Model and Specifications t DSH t DSH t t OSCH OSCS PPMX May 2011 Altera Corporation ...
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... For external I/O timing using standards other than LVTTL or for different drive strengths, use the I/O standard input and output delay adders in f For more information about each external timing parameters symbol, refer to AN629: Understanding Timing in Altera May 2011 Altera Corporation 9 Address Bits t t ...
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... May 2011 Altera Corporation C5, I5 Unit Max 14.0 ns 8.5 ns — ns — ns 8.6 ns — ps — ps — ns 118.3 MHz C5, I5 Unit Max 17 ...
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... The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency. (2) Not applicable to the F324 package of the 5M1270Z device. May 2011 Altera Corporation (Note 1) C4 Condition ...
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... May 2011 Altera Corporation C5, I5 Unit Max 11.2 ns 5.9 ns — ns — ns 7.4 ns — ps — ps — ns 201.1 MHz C5, I5 Unit Max 11 ...
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... I/O Standard Min Without Schmitt Trigger 3.3-V LVTTL With Schmitt Trigger May 2011 Altera Corporation Table 3–36 on page 3–25 list the adder delays associated with I/O timing parameters listed in SU Table 3–31. If you select an I/O standard other than 3.3-V LVTTL listed in Table 3– ...
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... May 2011 Altera Corporation Unit Unit ...
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... Table 3–36. IOE Programmable Delays for MAX V Devices Parameter Min Input Delay from Pin to Internal — Cells = 1 Input Delay from Pin to Internal — Cells = 0 May 2011 Altera Corporation Adders for Slow Slew Rate for MAX V Devices OD 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Max Min ...
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... MHz 200 MHz 150 MHz 120 MHz 304 MHz 5M40Z/ 5M80Z/ 5M160Z/ Unit 5M2210Z C4, C5, I5 304 MHz 304 MHz 304 MHz 304 MHz 200 MHz 200 MHz 150 MHz 120 MHz 304 MHz 304 MHz 200 MHz May 2011 Altera Corporation ...
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... ALTLVDS_TX instance). The actual performance of your LVDS_E_3R transmitter system must be attained through MAX the Quartus II timing analysis of the complete design. (2) For the input clock pin to achieve 304 Mbps, use I/O standard with V (3) This specification is based on external clean clock source. May 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z/5M1270Z/ Mode Min ...
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... V and above. CCIO Timing Model and Specifications 5M2210Z Unit C4, C5, I5 Max 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 55 % 0.2 UI 450 ps 450 ps May 2011 Altera Corporation ...
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... JTAG port valid output to high impedance JPXZ t Capture register setup time JSSU t Capture register hold time JSH t Update register clock to output JSCO t Update register high impedance to valid output JSZX May 2011 Altera Corporation t JCP t t JPSU JPH t JCL t JPZX JPCO t t JSSU ...
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... JPCO JPZX JPXZ Changes Updated Table 3–2, Table 3–15, Table 3–16, and Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40. Initial release. Document Revision History Min Max Unit — Table 3–33. May 2011 Altera Corporation ...