5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 117

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
Figure 7–10. Acknowledge on the I
January 2011 Altera Corporation
Data Output
By Transmitter
Data Output
By Receiver
SCL From
Master
Start Condition
S
Acknowledge
Acknowledged data transfer is a requirement of I
pulse to signify the acknowledge bit. The transmitter releases the SDA line (high)
during the acknowledge clock pulse.
The receiver (slave) must pull the SDA line low during the acknowledge clock pulse
so that SDA remains a stable low during the clock high period, indicating positive
acknowledgement from the receiver. If the receiver pulls the SDA line high during the
acknowledge clock pulse, the receiver sends a not-acknowledge condition indicating
that it is unable to process the last byte of data. If the receiver is busy (for example,
executing an internally-timed erase or write operation), it will not acknowledge any
new data transfer.
Device Addressing
After the start condition, the master sends the address of the particular slave device it
is requesting. The four most significant bits (MSBs) of the 8-bit slave address are
usually fixed while the next three significant bits (A
that define which device the master is accessing. The last bit of the slave address
specifies whether a read or write operation is to be performed. When this bit is set to
1, a read operation is selected. When this bit is set to 0, a write operation is selected.
The four MSBs of the slave address (A
defined on page 3 of the ALTUFM MegaWizard Plug-In Manager. The default value
for these four MSBs is 1010. The next three significant bits are defined using the three
A
to input pins in the design file and connect them to switches on the board. The other
option is to connect them to V
conserves pins.
2
, A
1
, A
0
input ports of the ALTUFM_I2C megafunction. You can connect these ports
2
C Bus
Figure 7–11
Figure 7–10
shows the slave address bits.
CC
shows the acknowledge condition on the I
and GND primitives in the design file, which
6
, A
5
, A
4
, A
2
3
C. The master must generate a clock
) are programmable and can be
2
, A
Not Acknowledge
Acknowledge
1
, A
0
) are device address bits
Acknowledgement
Clock Pulse For
MAX V Device Handbook
2
C bus.
7–15