5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 151

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
IEEE Std. 1149.1 Boundary-Scan Register
Figure 8–4. User I/O BSC with IEEE Std. 1149.1 BST Circuitry for MAX V Devices
Table 8–2. BSC Description for MAX V Devices
December 2010 Altera Corporation
Note to
(1) TDI, TDO, TMS, and TCK pins and all VCC and GND pin types do not have BSCs.
Pin Type
User I/O
Table
JTAG Pins and Power Pins
From or To Device
I/O Cell Circuitry
And/Or Logic Core
8–2:
Register
Capture
Output
OUTJ
Figure 8–4
Table 8–2
devices.
MAX V devices do not have BSCs for dedicated JTAG pins (TDI, TDO, TMS, and TCK)
and power pins (VCCINT, VCCIO, GNDINT, and GNDIO).
OUTJ
OEJ
INJ
OE Capture
Captures
Register
lists the capture and update register capabilities of all BSC within MAX V
shows the user I/O BSC for MAX V devices.
SHIFT
OEJ
SDI
0
1
0
1
0
1
Input Capture
(Note 1)
CLOCK
D
D
D
Output
Register
PIN_IN
Input
OE
Q
Q
Q
SDO
Capture
Registers
UPDATE
D
D
Output
OE
Q
Q
Update
Registers
PIN_OUT
Register
Update
Output
HIGHZ
0
1
MODE
0
1
0
1
OE Update
Register
PIN_OE
Drives
Global Signals
PIN_IN
PIN_OE
PIN_OUT
Input Update
Output
Buffer
Register
—
MAX V Device Handbook
Pin
user clocks
Includes
Notes
8–5