5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 123

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
Figure 7–16. Random Address Read Sequence
Figure 7–17. Sequential Read Sequence
January 2011 Altera Corporation
S – Start Condition
Sr – Repeated Start
P – Stop Condition
A – Acknowledge
S
S – Start Condition
Sr – Repeated Start
P – Stop Condition
A – Acknowledge
S
Address
Slave
Address
Slave
‘0’ (write)
Random Address Read
Random address read operation allows the master to select any byte location for a
read operation. The master first performs a “dummy” write operation by sending the
start condition, slave address, and byte address of the location it wishes to read. After
the ALTUFM_I2C megafunction acknowledges the slave and byte address, the master
generates a repeated start condition, the slave address, and the R/W bit is set to 1. The
ALTUFM_I2C megafunction then responds with acknowledge and sends the 8-bit
data requested. The master then generates a stop condition.
random address read sequence.
Sequential Read
Sequential read operation can be initiated by either the current address read operation
or the random address read operation. Instead of sending a stop condition after the
slave has transmitted one byte of data to the master, the master acknowledges that
byte and sends additional clock pulses (on the SCL line) for the slave to transmit data
bytes from consecutive byte addresses. The operation is terminated when the master
generates a stop condition instead of responding with an acknowledge.
shows the sequential read sequence.
R/W
‘0’ (write)
R/W
A
A
Address
Byte
Address
Byte
A
Sr
A
Address
Sr
Slave
Address
Slave
‘1’ (read)
R/W
‘1’ (read)
A
R/W
Data (n - bytes) + Acknowledgment (n - 1 bytes)
Data
A
From Master to Slave
From Slave to Master
From Master to Slave
From Slave to Master
A
Figure 7–16
Data
…
MAX V Device Handbook
Data
Figure 7–17
shows the
P
P
7–21