5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 139

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5M80ZT100C5N

Manufacturer Part Number
5M80ZT100C5N
Description
ALTERA
Manufacturer
Altera
Series
MAX Vr

Specifications of 5M80ZT100C5N

Cpld Type
FLASH
No. Of Macrocells
64
No. Of I/o's
79
Propagation Delay
7.5ns
Global Clock Setup Time
4.6ns
Frequency
118.3MHz
Supply Voltage Range
1.71V To 1.89V
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
80
Number Of Macrocells
64
Number Of Gates
-
Number Of I /o
79
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
Table 7–16. Parallel Interface Timing Parameters
January 2011 Altera Corporation
t
t
t
COMMAND
HNBUSY
HBUS
Symbol
The time required for the command signal (nREAD/nWRITE/nERASE)
to be asserted and held low to initiate a read/write/erase sequence
Maximum delay between command signal’s falling edge to the
nBUSY signal’s falling edge
The time that the data and address buses must be present at the
data input and address register ports after the command signal has
been asserted low
ALTUFM Parallel Interface Timing Specification
Figure 7–34
the parallel interface instruction signals. The nREAD, nWRITE, and nERASE signals are
active low signals.
Figure 7–34. Parallel Interface Timing Waveform
Instantiating Parallel Interface Using Quartus II ALTUFM_PARALLEL
Megafunction
Figure 7–35
interface instantiation in the Quartus II software.
Figure 7–35. ALTUFM_PARALLEL Megafunction Symbol for Parallel Interface Instantiation
Command
nBusy
Data or Address Bus
shows the timing specifications for the parallel interface.
shows the ALTUFM_PARALLEL megafunction symbol for a parallel
Description
t
HNBUSY
t
HBUS
t
COMMAND
Minimum (ns)
600
600
MAX V Device Handbook
Table 7–16
Maximum (ns)
3,000
300
lists
7–37

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