ADIS16400/PCBZ Analog Devices Inc, ADIS16400/PCBZ Datasheet - Page 10

• Manufacturer Part Number: ADIS16400/PCBZ
• Description: ADIS16400/PCB EVAL. BD. PB Free
• Manufacturer: Analog Devices Inc
• Series: iMEMS®, iSensor™r

Specifications of ADIS16400/PCBZ

• Sensor Type: Accelerometer, Gyroscope, Magnetometer, 3 Axis
• Sensing Range: ±18g, ±75°/sec, ±150°/sec, ±300°/sec, ±2.5gauss
• Interface: SPI Serial
• Sensitivity: 3.33mg/LSB, 0.0125 ~ 0.05°/sec/LSB, 0.5mgauss/LSB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Embedded: No
• Utilized Ic / Part: ADIS16400
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: ADIS16400
• Kit Application Type: Sensing - Navigation / Position
• Application Sub Type: Accelerometer / Gyroscope
• Kit Contents: Board, Manual
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADIS16400/ADIS16405
THEORY OF OPERATION
BASIC OPERATION
The ADIS16400/ADIS16405 are autonomous sensor systems
that start up after a valid power supply voltage is applied and
then begin producing inertial measurement data at the factory-
default sample rate of 819.2 SPS. After each sample cycle, the
sensor data loads into the output registers and DIO1 pulses,
providing a new data ready control signal for driving system-
level interrupt service routines. In a typical system, a master
processor accesses the output data registers through the SPI
interface, using the hook-up shown in Figure 9. Table 6
provides a generic functional description for each pin on the
master processor. Table 7 describes the typical master processor
settings normally found in a configuration register and used for
communicating with the ADIS16400/ADIS16405.
Table 6. Generic Master Processor Pin Names and Functions
Pin Name
SS
IRQ
MOSI
MISO
SCLK
Table 7. Generic Master Processor SPI Settings
Processor Setting
Master
SCLK Rate ≤ 2 MHz
CPOL = 1
CPHA = 1
MSB-First
16-Bit
1
The user registers provide addressing for all input/output
operations on the SPI interface. Each 16-bit register has two
7-bit addresses: one for its upper byte and one for its lower byte.
For burst mode, SCLK rate ≤ 1 MHz. For low power mode, SCLK rate ≤ 300 kHz.
SYSTEM
PROCESSOR
SPI MASTER
VDD
Figure 9. Electrical Hook-Up Diagram
I/O LINES ARE COMPATIBLE WITH
1
SCLK
MOSI
MISO
3.3V OR 5V LOGIC LEVELS
IRQ
SS
Description
The ADIS16400/ADIS16405 operate as a
slave.
Normal mode, SMPL_PRD[7:0] ≤ 0x08.
Clock polarity.
Clock phase.
Bit sequence.
Shift register/data length.
Function
Slave select
Interrupt request
Master output, slave input
Master input, slave output
Serial clock
6
3
5
4
7
CS
SCLK
DIN
DOUT
DIO1
10
13
ADIS16405
5V
11
SPI SLAVE
14
12
15
Rev. B | Page 10 of 20
Table 8 lists the lower byte address for each register, and Figure 10
shows the generic bit assignments.
READING SENSOR DATA
Although the ADIS16400/ADIS16405 produce data indepen-
dently, these operate as SPI slave devices that communicate with
system (master) processors using the 16-bit segments displayed
in Figure 11. Individual register reads require two such 16-bit
sequences. The first 16-bit sequence provides the read command
bit ( R /W = 0) and the target register address (A6 to A0). The
second sequence transmits the register contents (D15 to D0) on
the DOUT line. For example, if DIN = 0x0A00, the content of
XACCL_OUT shifts out on the DOUT line during the next 16-bit
sequence.
The SPI operates in full duplex mode, which means that the master
processor can read the output data from DOUT while using the
same SCLK pulses to transmit the next target address on DIN.
DEVICE CONFIGURATION
The user register memory map (Table 8) identifies configuration
registers with either a W (write only) or R/W (read/write).
Configuration commands also use the bit sequence displayed in
Figure 11. If the MSB is equal to 1, the last eight bits (DC7 to
DC0) in the DIN sequence load into the memory address
associated with the address bits (A5 to A0). For example, if DIN
= 0xA11F, then 0x1F loads into Address Location 0x21
(XACCL_OFF, upper byte) at the conclusion of the data frame.
Most of the registers have a backup location in nonvolatile flash
memory. The master processor must manage the backup function.
Set GLOB_CMD[3] = 1 (DIN = 0xBE04) to execute a manual
flash update (backup) operation, which copies the user registers
into their respective flash memory locations. This operation
takes 50 ms and requires the power supply voltage to be within
the specified limit to complete properly. The FLASH_CNT register
provides a running count of these events for managing the long-
term reliability of the flash memory.
BURST MODE DATA COLLECTION
Burst mode data collection offers a more efficient method for
collecting data from the ADIS16400/ADIS16405. In sequential data
cycles (each separated by one SCLK period), all output registers
clock out on DOUT. This sequence starts when the DIN sequence
is 0011 1110 0000 0000 (0x3E00). Next, the contents of each output
register are output from DOUT, starting with SUPPLY_OUT
and ending with AUX_ADC (see Figure 12). The addressing
sequence shown in Table 8 determines the order of the outputs
in burst mode.
15
14
13
UPPER BYTE
12
Figure 10. Output Register Bit Assignments
11
10
9
8
7
6
5
LOWER BYTE
4
3
2
1
0