UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 85
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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3.4.4 Short direct addressing
Effective address
[Function]
[Operand format]
[Description example]
[Illustration]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special
function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. See the [Illustration] shown below.
LB1 EQU 0FE30H ; Defines FE30H by LB1.
MOV LB1, A
When 8-bit immediate data is 20H to FFH,
When 8-bit immediate data is 00H to 1FH,
:
saddr
saddrp
Identifier
15
7
1
Operation code
1
; When LB1 indicates FE30H of the saddr area and the value of register A is transferred to
1
that address
saddr-offset
Immediate data that indicate label or FE20H to FF1FH
Immediate data that indicate label or FE20H to FF1FH (even address only)
OP code
1
1
1
CHAPTER 3 CPU ARCHITECTURE
1
1
0
User’s Manual U17260EJ6V0UD
0
8 7
1
0
= 1
= 0
1
1
1
1
0
0
Description
0
0
1
0
0
0
OP code
30H (saddr-offset)
0
Short direct memory
85
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