UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 286
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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<R>
<R>
<R>
286
(TOLEV1 = 0)
<1> The count operation is enabled by setting TMHEn = 1. Start the 8-bit timer counter Hn by masking one count
<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous
<3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the value of the 8-bit timer
<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the
<5> When the values of the 8-bit timer counter Hn and the CMP1n register after the change match, an inactive
<6> Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal to the default and PWM
Count clock
counter Hn
8-bit timer
INTTMH1
CMP01
CMP11
TMHE1
TOH1
clock to count up. At this time, PWM output outputs an inactive level.
to the count clock.
counter Hn is cleared, an active level is output, and the INTTMHn signal is output.
values of the 8-bit timer counter Hn and the CMP1n register before the change match, the value is
transferred to the CMP1n register and the CMP1n register value is changed (<2>’).
However, three count clocks or more are required from when the CMP1n register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
level is output. The 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
output to an inactive level.
Remark n = 0, 1
00H 01H 02H
<1>
(e) Operation by changing CMP1n (CMP1n = 02H → 03H, CMP0n = A5H)
02H
Figure 9-12. Operation Timing in PWM Output Mode (4/4)
80H
<2>
CHAPTER 9 8-BIT TIMERS H0 AND H1
A5H 00H 01H 02H 03H
02H (03H)
<3>
User’s Manual U17260EJ6V0UD
<2>’
<4>
A5H
03H
A5H 00H 01H 02H 03H
<5>
A5H 00H
<6>
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