UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 144
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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Address: FF9FH
OSCCTL
Symbol
Note
Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
Remark f
EXCLK
EXCLK
AMPH
Figure 6-2. Format of Clock Operation Mode Select Register (OSCCTL)
<7>
0
0
1
1
0
1
After reset: 00H
EXCLKS and OSCSELS are used in combination with XTSTART (bit 6 of the processor
clock control register (PCC)). See (3) Setting of operation mode for subsystem clock
pin.
XH
2. Set AMPH before setting the peripheral functions after a reset release. The value
3. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is
4. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7
: High-speed system clock oscillation frequency
1 MHz ≤ f
10 MHz < f
OSCSEL
OSCSEL
exceeds 10 MHz.
of AMPH can be changed only once after a reset release. When the high-speed
system clock (X1 oscillation) is selected as the CPU clock, supply of the CPU
clock is stopped for 4.06 to 16.12
speed system clock (external clock input) is selected as the CPU clock, supply of
the CPU clock is stopped for the duration of 160 external clocks after AMPH is
set to 1.
stopped for 4.06 to 16.12
high-speed oscillation clock is selected as the CPU clock, or for the duration of
160 external clocks when the high-speed system clock (external clock input) is
selected as the CPU clock. When the high-speed system clock (X1 oscillation) is
selected as the CPU clock, the oscillation stabilization time is counted after the
STOP mode is released.
(MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or
the external clock from the EXCLK pin is disabled).
<6>
0
1
0
1
XH
XH
≤ 10 MHz
R/W
CHAPTER 6 CLOCK GENERATOR
High-speed system clock
I/O port mode
X1 oscillation mode
I/O port mode
External clock input
mode
≤ 20 MHz
EXCLKS
pin operation mode
<5>
User’s Manual U17260EJ6V0UD
Note
OSCSELS
<4>
Operating frequency control
µ
s after the STOP mode is released when the internal
Note
I/O port
Crystal/ceramic resonator connection
I/O port
I/O port
µ
3
0
s after AMPH is set to 1. When the high-
P121/X1 pin
2
0
External clock input
P122/X2/EXCLK pin
1
0
AMPH
<0>
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