UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 301
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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11.2 Configuration of Watchdog Timer
WINDOW1 and WINDOW0
The watchdog timer includes the following hardware.
How the counter operation is controlled, overflow time, and window open period are set by the option byte.
of option byte (0080H)
WDCS2 to WDCS0 of
option byte (0080H)
CPU access signal
WDTON of option
Remark For the option byte, see CHAPTER 25 OPTION BYTE.
f
Window open period
Controlling counter operation of watchdog timer
Overflow time of watchdog timer
RL
byte (0080H)
/2
Control register
Setting of Watchdog Timer
controller
Clock
input
Item
Table 11-2. Setting of Option Bytes and Watchdog Timer
Watchdog timer enable
register (WDTE)
Figure 11-1. Block Diagram of Watchdog Timer
Clear, reset control
Table 11-1. Configuration of Watchdog Timer
counter
17-bit
CHAPTER 11 WATCHDOG TIMER
Watchdog timer enable register (WDTE)
Count clear
signal
User’s Manual U17260EJ6V0UD
2
2
10
17
error detector
CPU access
/f
/f
RL
RL
Internal bus
to
determination
Selector
Window size
Bits 6 and 5 (WINDOW1, WINDOW0)
Bit 4 (WDTON)
Bits 3 to 1 (WDCS2 to WDCS0)
signal
Configuration
Overflow
signal
Option Byte (0080H)
controller
output
Reset
Internal reset signal
301
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