UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 598
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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Notes 1. This connection is designed assuming that the reset signal is output from the N-ch open-drain buffer
Connect the FLMD0 pin as follows when performing self programming by means of on-chip debugging.
Figure 27-3. Connection of FLMD0 Pin for Self Programming by Means of On-Chip Debugging
2. This is the processing of the pin when OCD1B/P32 is set as the input port (to prevent the pin from being
3. Make pull-down resistor 470 Ω or more (10 kΩ: recommended).
4. Characters without parentheses represent the QB-78K0MINI name, and those within parenthesis the
(output resistance: 100 Ω or less). For details, refer to QB-78K0MINI User’s Manual (U17029E) or QB-
MINI2 User’s Manual (U18371E).
left opened when not connected to QB-78K0MINI or QB-MINI2).
QB-MINI2 name.
Figure 27-2. Connection Example of QB-78K0MINI or QB-MINI2 and
Target connector
(10-pin)
Target connector
RESET_IN
X2 (DATA)
RESET_OUT
X1 (CLK)
FLMD0
FLMD0
CHAPTER 27 ON-CHIP DEBUG FUNCTION (
R.F.U.
R.F.U.
GND
GND
Note 4
Note 4
V
Note 1
DD
(Open)
(Open)
(When OCD1A/P31 and OCD1B/P32 Are Used)
V
DD
V
User’s Manual U17260EJ6V0UD
DD
(Recommended)
3 to 10 kΩ
(Recommended)
10 kΩ
Note 3
Note 2
Note 3
V
DD
1 kΩ
(Recommended)
1 k Ω (recommended)
10 k Ω (recommended)
PD78F0537D ONLY)
V
DD
µ
Reset circuit
Reset signal
Target device
V
OCD1B/P32
OCD1A/P31
GND
RESET
FLMD0
Port
FLMD0
PD78F0537D
DD
µ
PD78F0537D
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