ML610Q428-NNNTBZ03A7 Rohm Semiconductor, ML610Q428-NNNTBZ03A7 Datasheet - Page 98

• Manufacturer Part Number: ML610Q428-NNNTBZ03A7
• Description: MCU 8BIT 48K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q428-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.2.6
The high-speed clock generation circuit is activated in 500Hz RC oscillation mode by power-on reset generation.
As a result of the occurrence of power-on reset, the circuit goes into system reset mode and then shifts to program
operating mode after the elapse of the high-speed RC oscillation start time (T
(Count: 8192) of the high-speed oscillation clock (OSCLK) and at the same time, a high-speed clock (HSCLK) is
supplied to the peripheral circuits.
Figure 6-9 shows the waveforms of the high-speed clock generation circuit at power on. For the high-speed RC
oscillation start time (T
The high-speed clock generation circuit allows selection of an oscillation mode and start/stop of oscillation by using the
frequency control registers 0 and 1 (FCON0 and FCON1).
Oscillation can be started by setting the ENOSC bit to “1” after selecting a high-speed oscillation mode in FCON0 and
a high-speed oscillation frequency. After the start of oscillation, HSCLK starts supply of a clock to the peripheral
circuits following the elapse of the high-speed oscillation start period (T
stabilization period of the high-speed oscillation clock (OSCLK).
The high-speed clock generation circuit stops oscillation when it shifts to a STOP mode by the software. When the
STOP mode is released by external interrupt, HSCLK supplies clocks to peripheral circuits following the elapse of the
high-speed oscillation start period (T
high-speed clock (OSCLK). The oscillation stabilization period is the duration of 128 clock pulses in 500 kHz RC
oscillation mode and external clock input mode and the duration of 4096 clock pulses in the crystal/ceramic oscillation
mode and PLL oscillation mode.
Operation of High-Speed Clock Generation Circuit
Figure 6-9 Operation of High-Speed Clock Generation Circuit at Power-On
High-speed oscillation
Power supply V
High-speed clock
RC
clock waveform
), see Appendix C, “Electrical Characteristics”.
System clock
SYSCLK
RESET
HSCLK
DD
RC
/T
XTH
T
/T
RC
: Oscillation start time
PLL
High-speed oscillation
Count: 8192
) in each mode and the oscillation stabilization period of the
High-speed oscillation clock waveform
6 – 12
CPU start
RC
HSCLK waveform
SYSCLK waveform
ML610Q428/ML610Q429 User’s Manual
/T
XTH
Chapter 6 Clock Generation Circuit
RC
/T
) and the oscillation stabilization time
PLL
) in each mode and the oscillation