ML610Q428-NNNTBZ03A7 Rohm Semiconductor, ML610Q428-NNNTBZ03A7 Datasheet - Page 145
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ML610Q428-NNNTBZ03A7
Manufacturer Part Number
ML610Q428-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q428-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
ROHM
Quantity:
750
Company:
Part Number:
ML610Q428-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q428-NNNTBZ03A7 PDF datasheet #2
- ML610Q428-NNNTBZ03A7 PDF datasheet #3
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10.2.10 PWM2 Counter Registers (PW2CH, PW2CL)
Address: 0F0B4H
Access: R/W
Access size: 8 bits
Initial value: 00H
Address: 0F0B5H
Access: R/W
Access size: 8 bits
Initial value: 00H
PW2CL and PW2CH are special function registers (SFRs) that function as 16-bit binary counters.
When data is written to either PW2CL or PW2CH, PW2CL and PW2CH is set to “0000H”. The data that is written is
meaningless.
When data is read from PW2CL, the value of PW2CH is latched. When reading PW2CH and PW2CL, use a word type
instruction or pre-read PW2CL.
The contents of PW2CH and PW2CL during PWM operation cannot be read depending on the combination of the
PWM clock and system clock. Table 10-3 shows PW2CH and PW2CL read enable/disable for each combination of the
PWM clock and system clock.
PW2DH
At reset
At reset
PW2CL
R/W
R/W
External clock
PWM clock
HTBCLK
HTBCLK
Table 10-3 PW2CH and PW2CL Read Enable/Disable during PWM2 Operation
LSCLK
LSCLK
P2CK
P2C15
P2C7
R/W
R/W
7
0
7
0
P2C14
P2C6
R/W
R/W
System clock
0
0
6
6
SYSCLK
HSCLK
HSCLK
HSCLK
LSCLK
LSCLK
LSCLK
P2C13
P2C5
R/W
R/W
5
0
5
0
Read enabled
Read enabled. However, to prevent the reading of undefined data
during counting, read consecutively PW2CH or PW2CL twice
until the last data coincides the previous data.
Read disabled
Read enabled
Read disabled
P2C12
P2C4
R/W
R/W
10 – 11
4
0
4
0
PW2CH and PW2CL read enable/disable
P2C11
P2C3
R/W
R/W
3
0
3
0
ML610Q428/ML610Q429 User’s Manual
P2C10
P2C2
R/W
R/W
2
0
2
0
P2C1
P2C9
R/W
R/W
1
0
1
0
Chapter 10 PWM
P2C0
P2C8
R/W
R/W
0
0
0
0
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