LFEC3E-5TN144C Lattice, LFEC3E-5TN144C Datasheet - Page 69

• Manufacturer Part Number: LFEC3E-5TN144C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs Pb-Free
• Manufacturer: Lattice

Specifications of LFEC3E-5TN144C

• Number Of Logic Blocks: 384
• Number Of Macrocells: 3100
• Number Of Programmable I/os: 97
• Data Ram Size: 56320
• Delay Time: 5 ns
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 3100
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
Notes:
1. “n” is a Row/Column PIC number
2. The DDR interface is designed for memories that support one DQS strobe per eight bits of
3. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descrip-
data. In some packages, all the potential DDR data (DQ) pins may not be available.
tions table.
PICs Associated
with DQS Strobe
PIO Within PIC
4-3
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
LatticeECP/EC Family Data Sheet
DDR Strobe (DQS) and
Data (DQ) Pins
[Edge]DQSn
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Pinout Information